Calibre LVS error "Bad component subtype"

[hustwill]

I use Cadence composer draw a "BUF" schematic, and lead to the layout XL(virtuoso XL) BUF layout.
But when I did the LVS check with Calibre, it report the errors:
bad component subtype:
layout: source
MP(P18LL) MP(P18)

I don't know how to solve the problem.
The layout was connected from the schematic by the virtuoso XL, and the MOS was from the PDK.
Can anyone give some advice?
Thank you!

 

[Saravanan.G]

If u check the calibre rule file the layout PMOS device is extracted as P18LL , and the netlist(cdl) it is P18 that is the reason are getting this.
both should be identical.
first check if there is a device extraction as P18 in rule file.
since u r using PDK the is no chance for layer drawing mistakes
make sure u re using right type of device for corresponding schematic before trying the solutions below.

1 add a match table for devices
2 change the rule file to extract device as P18
3 change in the netlist to P18LL

 

[aniladavally]

For matching devices you can add the following line to your rule file

LVS MAP DEVICE MP(P18LL) MP(P18) LAYOUT

Cheers!

 

[hesam_ahmadi]

thanks aniladavally :smile: , but i seems that LAYOUT is not needed and "LVS MAP DEVICE MP(P18LL) MP(P18)" is ok
i used LVS MAP DEVICE D(PN) D(DP) and works