hustwill
Newbie level 4

I use Cadence composer draw a "BUF" schematic, and lead to the layout XL(virtuoso XL) BUF layout.
But when I did the LVS check with Calibre, it report the errors:
bad component subtype:
layout: source
MP(P18LL) MP(P18)
I don't know how to solve the problem.
The layout was connected from the schematic by the virtuoso XL, and the MOS was from the PDK.
Can anyone give some advice?
Thank you!
But when I did the LVS check with Calibre, it report the errors:
bad component subtype:
layout: source
MP(P18LL) MP(P18)
I don't know how to solve the problem.
The layout was connected from the schematic by the virtuoso XL, and the MOS was from the PDK.
Can anyone give some advice?
Thank you!