I am in need of a Book that teaches me how to code and synthesize Verilog using Synopsys DC. I need something like Weng Fook Lee's VHDL book based on Synopsys. Or if there is some online material or a tutorial that gives me an overview of DC for running verilog, that would be fine too. I tried coding Verilog and ended up having some errors and some commands like the "initial" not being accepted.
There are some books posted on this forum like HDL chip design by smith and verilog synthesis primer by J basker and Adavanced ASIC synthesis book. The combination of these three should be able to get code and run dc shell
I give you an advice. You are better to learn synthesized verilog than sythesis using tool's compiler if you are the first time to study HDL language. And you want to learn how to code the synthesized verilog, a book is for your reference. I learned the sythesized verilog and behavior verilog from this book. The book name is "A guide to digital design and sythesis, SAMIR PALNITKAR, SunSoft Press"
You can read the Synopsys's Verilog HDL synthsis text which will tell you how to write in verilog and systhsize.But I think you should first read simple book about verilog and testbench.The question you ask is the most simple phenomenon in the IC logic desing.
Not much has changed in the area of Verilog Synthesis in 20 years. The only feature I see people use from Verilog-2001 is always @(*). If you want to go the updated route, look at "SystemVerilog for Design"
Product based books are never published to my understanding. Product focus books are only the documentation that goes with the product and its installation.