Basic Verilog doubt timing

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firozjdang

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Whats the difference between #5 q <= d; and q <= #5 d;
I tried the simulations but just got confused, help appreciated.
Thanks!
 

First statement assigns the current value of d to q after 5 time units. While second statement assigns the value d after 5 units to q. It is well explained in "Verilog HDL" by samir palintkar with example and timing diagram.
 
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