jaromirkolouch
Newbie level 3
In Verilog, a commonly known rule states that in always blocks, only blocking or only nonblocking assignments should be used, not a mix in one block.
Could anybody tell whether a similar rule is valid in SystemVerilog? I have seen worked-out designs of an experienced designer with a mixture of assignments type in one block but I did not find a syntactical rule about it in SV.
Thank in advance.
Could anybody tell whether a similar rule is valid in SystemVerilog? I have seen worked-out designs of an experienced designer with a mixture of assignments type in one block but I did not find a syntactical rule about it in SV.
Thank in advance.