error inside the always block due to module instantiation?

[ryan1122]

I want to perform complex multiplication using Verilog. Here I have called a module inside an always block. But, I got an error in the line "adder d(acc,m,clk,rst,out1);" (line 29) as error: syntax error near "adder". I tried to solve this problem in different ways but still showing the same error. Please help me to solve the error. The code for the specific module where the error is present is attached.

 

[TrickyDicky]

A module cannot be instantiated inside an always block. Think as a module as a chip on circuit board, and an always block as the behaviour of a circuit on a board. You cannot add and take away chips on the board conditionally, they must be there all the time.