Assignments in SystemVerilog always block

[jaromirkolouch]

In Verilog, a commonly known rule states that in always blocks, only blocking or only nonblocking assignments should be used, not a mix in one block.
Could anybody tell whether a similar rule is valid in SystemVerilog? I have seen worked-out designs of an experienced designer with a mixture of assignments type in one block but I did not find a syntactical rule about it in SV.
Thank in advance.

 

[mrflibble]

You might want to check the new always_ff, always_comb and always_latch blocks. So for example this here link.

 

[jaromirkolouch]

You might want to check the new always_ff, always_comb and always_latch blocks. So for example this here link.

Thank for reply. I am, of course, aware of the always_ff, always_latch and always_comb blocks (maybe, I have had to write it in my question but I supposed it is obvious). Nevertheless, there is no answer to my question in the link.

 

[mrflibble]

Thank for reply. I am, of course, aware of the always_ff, always_latch and always_comb blocks (maybe, I have had to write it in my question but I supposed it is obvious). Nevertheless, there is no answer to my question in the link.

Heheh, no way that I was going to assume that you knew about it. Of course it seems reasonable. But then again, you should read some other posts on this forum and then you'd come to the conclusion that no matter how trivial ... best to make NO assumptions whatsoever.

Now that we have that assumption out of the way ... yes in SV it remains the same. In a single block, don't mix blocking / non-blocking.

 

[jaromirkolouch]

Heheh, no way that I was going to assume that you knew about it. Of course it seems reasonable. But then again, you should read some other posts on this forum and then you'd come to the conclusion that no matter how trivial ... best to make NO assumptions whatsoever.

Now that we have that assumption out of the way ... yes in SV it remains the same. In a single block, don't mix blocking / non-blocking.

Thank again. I supposed the rules of Verilog remain valid in SV but i wonder that the mentioned experienced and well-known designer and SV textbook author does the mix in his book without commenting or explanation.