thiagu_comp
Member level 1
Hi,
Can someone explain ASIC emulation in detail? I know that it is quick method to validate the ASIC design before fab. It involves porting of original design to hardware and driving the stimulus. This increases the speed of verification compared to simulation. How is it different from prototyping? I had worked in prototying, where the ASIC is partitioned into multiple FPGAs depending on complexity and stimulus is driven in real time. Can somebody please explain. I am looking for specific answers to questions like - Does emulation involve FPGAs? or is it porting of system level model to a high end processor which mimics a ASIC? Where does the HW RTL and SW code sit during emulation? From where the stimulus is provided?
Can someone explain ASIC emulation in detail? I know that it is quick method to validate the ASIC design before fab. It involves porting of original design to hardware and driving the stimulus. This increases the speed of verification compared to simulation. How is it different from prototyping? I had worked in prototying, where the ASIC is partitioned into multiple FPGAs depending on complexity and stimulus is driven in real time. Can somebody please explain. I am looking for specific answers to questions like - Does emulation involve FPGAs? or is it porting of system level model to a high end processor which mimics a ASIC? Where does the HW RTL and SW code sit during emulation? From where the stimulus is provided?