Any tool to get timing library

[iamczx]

hi members,
After layout ,we can get many materials,such as sdf,gdsII ..
And I want to know,if there is any tool can extract the timing information and produce the timing library which can be used by synopsys design compiler?

just like the following format:

library(USERLIB) {
	delay_model		: table_lookup;
	revision		: 1.1;	
	date			: "2004-10-21 02:36:28Z";
	time_unit		: "1ns";
	voltage_unit		: "1V";
	current_unit		: "1mA";
	leakage_power_unit	: "1mW";
	nom_process		: 1;
	nom_temperature		: 125.000;
	nom_voltage		: 1.620;
	capacitive_load_unit	 (1,pf);

	pulling_resistance_unit	        : "1kohm";

	/* additional header data */
	default_cell_leakage_power      : 0;
	default_fanout_load		: 1;
	default_inout_pin_cap		: 0.005;
	default_input_pin_cap		: 0.005;
	default_output_pin_cap		: 0.0;
	default_max_transition		: 4.000;
......................

thanks in advance

 

[wangkl]

Someone advised to use Primetime to generate an ExtractTimingModel
BestRegards

 

[ryang]

Almost any STA analysis can generate a timing library. THe library format can be Synopsys Liberty library format or Cadence TLF library format

Just check your sta tool manual.

 

[act3eee]

AFAIK, Cadence does not have any tools which could output the synopsys lib format.

 

[marksile]

The tools of synopsys and the cadence aren't get timing library, timing library can only get from the manufactory. STA and PrimTime are only used as anaysis timing of circuit, it can't get timing library.

 

[iamczx]

I am confused after read the replies....

Does primetime can do the job I want?
If it can , what steps should i follow?

thanks again.

Added after 13 minutes:

Maybe I should add something:
the foundry provide the cell's timing library..
And if you design something, you also want build the timing library of your design---which is the same format with the foundry's -----,what tools should be used to do this job?

 

[ecijun]

synopsys star-mtb