Re: Physical Synthesis
mami_hacky said:
Then, Is it possible to perform Physical Synthesis and optimization for FPGAs using Synopsys Tools? What for ASICs?
Yes. You can use physical synthesis technique to do the FPGA synthesis.
Actually, $ynplicity has already make this idea into product (@mplify physical optimizer).
Using the physical information during the optimization (i.e. do the logic optimization & placement at the same time) majorly focus on timing closure.
As the process shrinking or in the case of FPGA architecture, the wire delay is growing longer than the cell/gate delay.
Typically, the logic synthesizer estimates the propagation delay based on wire-load model, and the wire loading (and therefore the wire delay) may be very different after the backend P&R tool doing the P&R.
In order to achieve the "timing convergence" more quickly, $ynopsys, $ynplicity, M@gama, ... these EDA tool venders have introduced new way to do the logic optimization.
Phy$ical compiler, @mplify physical optimizer and Bl@st chip (gain-based synthesis) are these tools.
But remember: Phy$ical compiler still solves the "ASIC synthesis" (i.e. multiple-level logic optimization) problem ! Not the "FPGA synthesis" (i.e. two-level logic optimization) problem !
The mapping & optimization performance of the Phy$ical compiler should still poor than the $ynpilfy pro (and, of course the @mplify) in the FPGA synthesis.