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Can design compiler do FPGA synthesis? I mean if there are
the library cells for those FPGA devices, could we use DC
instead of FPGA compiler. I am more familar with traditional
scripts than the graphics GUI.
I thank that you will fail to do that! fpga and asic 's synthesis is different.
Why syno&sys's asic synthesis is the best tools and it's fpga compiler is not the best? the priciple of synthesis of asic and fpga is so different!
Design-Compiler with FPGA library can do FPGA synthesis. But the Quality of Result (QoR) is not good. For ASIC (cell-base) DC and Incentia can do good job . For FPGA , the first choice is Synplify Pro .
Re: Already have FPGA compiler, why need Design Compiler (DC
Buzkiller says "DC is for ASIC synthesis, FPGA Compiler is for FPGA synthesis."
Because ASIC synthesis finally maps to standard cell, and is a problem of multi-level logic optimization.
By contrast, FPGA synthesis will map to the basic cell(unit) of the specific FPGA architecture, and is a problem of 2-level logic optimization.
One major difference is: almost each standard cell has only one output port (no matter how many input ports this cell has) but the basic FPGA unit usually has several outputs.
So the best algorithm for ASIC synthesis is not exactly the best for FPGA.
And for a NP-hard problem, there is no "best" solution, only "optimal" exists.
Of course, you can use Design Compiler to do the FPGA synthesis or use FPGA Compiler to do the ASIC synthesis, if your constraints (area & timing) are very easy to meet.
Yes. You can use physical synthesis technique to do the FPGA synthesis.
Actually, $ynplicity has already make this idea into product (@mplify physical optimizer).
Using the physical information during the optimization (i.e. do the logic optimization & placement at the same time) majorly focus on timing closure.
As the process shrinking or in the case of FPGA architecture, the wire delay is growing longer than the cell/gate delay.
Typically, the logic synthesizer estimates the propagation delay based on wire-load model, and the wire loading (and therefore the wire delay) may be very different after the backend P&R tool doing the P&R.
In order to achieve the "timing convergence" more quickly, $ynopsys, $ynplicity, M@gama, ... these EDA tool venders have introduced new way to do the logic optimization.
Phy$ical compiler, @mplify physical optimizer and Bl@st chip (gain-based synthesis) are these tools.
But remember: Phy$ical compiler still solves the "ASIC synthesis" (i.e. multiple-level logic optimization) problem ! Not the "FPGA synthesis" (i.e. two-level logic optimization) problem !
The mapping & optimization performance of the Phy$ical compiler should still poor than the $ynpilfy pro (and, of course the @mplify) in the FPGA synthesis.