Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Already have FPGA compiler, why need Design Compiler (DC)?

Status
Not open for further replies.

dd2001

Full Member level 4
Joined
Apr 14, 2002
Messages
236
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
1,912
Already have FPGA compiler, why need Design Compiler (DC)? what is differences ?
 

buzkiller

Member level 4
Joined
Dec 31, 1999
Messages
75
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
602
DC is for ASIC synthesis, FPGA Compiler is for FPGA synthesis.

regards,
Buzkiller.
 

SVTONY

Member level 1
Joined
Apr 10, 2002
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
186
Design Compiler

Can design compiler do FPGA synthesis? I mean if there are
the library cells for those FPGA devices, could we use DC
instead of FPGA compiler. I am more familar with traditional
scripts than the graphics GUI.
 

z81203

Full Member level 5
Joined
Aug 1, 2001
Messages
308
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Activity points
2,356
You can do that, but it's not a good choice.
DC is for ASIC's gate, FC is for FPGA & EPLD's CLB.
 

armer

Member level 5
Joined
Mar 29, 2002
Messages
84
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
576
dc

I thank that you will fail to do that! fpga and asic 's synthesis is different.
Why syno&sys's asic synthesis is the best tools and it's fpga compiler is not the best? the priciple of synthesis of asic and fpga is so different!
 

shell3

Member level 1
Joined
Mar 28, 2002
Messages
35
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
303
Synthesis for FPGA and ASIC require totally different algoriths. So the two
tools are differents.
 

S0933263236

Junior Member level 1
Joined
Jul 20, 2002
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Taiwan
Activity points
78
Design-Compiler with FPGA library can do FPGA synthesis. But the Quality of Result (QoR) is not good. For ASIC (cell-base) DC and Incentia can do good job . For FPGA , the first choice is Synplify Pro .
:D
 

lipton

Member level 2
Joined
Jul 14, 2002
Messages
46
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
244
Basically FPGA Compiler is a version of DC tweaked for FPGA synthesis.
Synopsys never bothered to develop a pure FPGA engine.
 

armer

Member level 5
Joined
Mar 29, 2002
Messages
84
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
576
FPGA asic

I don't think that fpga is only a tweaked version of dc_compile, synopsys indeed develop pure fpga engine!
 

lipton

Member level 2
Joined
Jul 14, 2002
Messages
46
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
244
It's hard to beleive that same engineers who did such a good job on the ASIC engine, whould do such a bang-up job on FPGA. It must be some quick tweak.
 

joe2moon

Full Member level 5
Joined
Apr 19, 2002
Messages
280
Helped
19
Reputation
38
Reaction score
7
Trophy points
1,298
Location
MOON
Activity points
3,749
Re: Already have FPGA compiler, why need Design Compiler (DC

Buzkiller says "DC is for ASIC synthesis, FPGA Compiler is for FPGA synthesis."

Yes.
Because ASIC synthesis finally maps to standard cell, and is a problem of multi-level logic optimization.
By contrast, FPGA synthesis will map to the basic cell(unit) of the specific FPGA architecture, and is a problem of 2-level logic optimization.

One major difference is: almost each standard cell has only one output port (no matter how many input ports this cell has) but the basic FPGA unit usually has several outputs.
So the best algorithm for ASIC synthesis is not exactly the best for FPGA.
And for a NP-hard problem, there is no "best" solution, only "optimal" exists. :eek:

ps:
Of course, you can use Design Compiler to do the FPGA synthesis or use FPGA Compiler to do the ASIC synthesis, if your constraints (area & timing) are very easy to meet.
 

mami_hacky

Full Member level 6
Joined
Mar 28, 2002
Messages
337
Helped
18
Reputation
36
Reaction score
11
Trophy points
1,298
Location
Some where
Activity points
3,428
Physical Synthesis

Then, Is it possible to perform Physical Synthesis and optimization for FPGAs using Synopsys Tools? What for ASICs?
 

kwkam

Full Member level 5
Joined
Feb 25, 2002
Messages
276
Helped
30
Reputation
60
Reaction score
13
Trophy points
1,298
Location
Somewhere on earth
Activity points
1,878
FPGA is different from the ASIC.

Inside the FPGA, all function block is fixed. The compiler is use to route the block into right sequence. There is why we need a large FPGA chip to implement a small logic.

For ASIC, we have lots of freedom to to the job
 

joe2moon

Full Member level 5
Joined
Apr 19, 2002
Messages
280
Helped
19
Reputation
38
Reaction score
7
Trophy points
1,298
Location
MOON
Activity points
3,749
Re: Physical Synthesis

mami_hacky said:
Then, Is it possible to perform Physical Synthesis and optimization for FPGAs using Synopsys Tools? What for ASICs?
Yes. You can use physical synthesis technique to do the FPGA synthesis. :D

Actually, $ynplicity has already make this idea into product (@mplify physical optimizer).

Using the physical information during the optimization (i.e. do the logic optimization & placement at the same time) majorly focus on timing closure.
As the process shrinking or in the case of FPGA architecture, the wire delay is growing longer than the cell/gate delay.
Typically, the logic synthesizer estimates the propagation delay based on wire-load model, and the wire loading (and therefore the wire delay) may be very different after the backend P&R tool doing the P&R.

In order to achieve the "timing convergence" more quickly, $ynopsys, $ynplicity, M@gama, ... these EDA tool venders have introduced new way to do the logic optimization.
Phy$ical compiler, @mplify physical optimizer and Bl@st chip (gain-based synthesis) are these tools.

But remember: Phy$ical compiler still solves the "ASIC synthesis" (i.e. multiple-level logic optimization) problem ! Not the "FPGA synthesis" (i.e. two-level logic optimization) problem !

The mapping & optimization performance of the Phy$ical compiler should still poor than the $ynpilfy pro (and, of course the @mplify) in the FPGA synthesis.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top