Jayson
Full Member level 4
Hi all,
Is there an advantage to writing testbenches in Verilog (i.e. easier, faster?) than in VHDL.
Recently I saw code in VHDL but the testbenches were written in Verilog, is there a reason somebody would write a testbench in Verilog rather than VHDL? Is Verilog better suited for testbenches?
Is there an advantage to writing testbenches in Verilog (i.e. easier, faster?) than in VHDL.
Recently I saw code in VHDL but the testbenches were written in Verilog, is there a reason somebody would write a testbench in Verilog rather than VHDL? Is Verilog better suited for testbenches?