Advantages of writing testbenches in Verilog rather than in VHDL

[Jayson]

Hi all,

Is there an advantage to writing testbenches in Verilog (i.e. easier, faster?) than in VHDL.

Recently I saw code in VHDL but the testbenches were written in Verilog, is there a reason somebody would write a testbench in Verilog rather than VHDL? Is Verilog better suited for testbenches?

 

[sree205]

Verilog testbenches

i think its possible to access internal registers with the instances for submodules using verilog.

e.g.

module_name instance_name(.port(wire))

in this case, inside the testbench, its possible to access and modify the internal register by,

instance_name.internal_reg <= value;

this is what i found lacking in vhdl. this might be one of the reasons.

 

[xiexie57]

Verilog testbenches

I thinks verilog better suited for testbenches.

 

[zhangpengyu]

Verilog testbenches

I think is the same.
Some higher level languages such as E,vera and systemverilog is better to write testbenches.

 

[spauls]

Re: Verilog testbenches

I think because of interaction with Software languages (PLI) etc is better in verilog.

 

[hys]

Re: Verilog testbenches

Its the same whether u use VHDL or Verilog for testbench, it is just the comfort level that an individual has over any those languages.

VHDL also has FLI which is on par with PLI of verilog.

These days HVLs have come into the picture.... and either Specman-e or Vera is used for testbench purpose..... But in future Vera is going to phase out... and System Verilog will take its place...

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet

 

[alpeshchokshi]

Re: Verilog testbenches

ya due to many features of verilog compare to vhdl is used for testbenches...
apart from this for complex SOC design the vera and system verilog is widely used language for verification

 

[aji_vlsi]

Re: Verilog testbenches

Harish,
I don't believe it is the same whether you use VHDL or Verilog for Testbench, there is a great deal of difference especially in TB. With plain Verilog-VHDL, VHDL is better as it has higher level data types, function overloading etc.

With SystemVerilog however, Verilog/SV has gone way ahead of VHDL for TB - mainly due to OOP, assertions, coverage etc. Even recently approved VHDL standard doesn't come even close.

Its the same whether u use VHDL or Verilog for testbench, it is just the comfort level that an individual has over any other those.

I would agree with you - it depends on the comfort level.

VHDL also has FLI which is on par with PLI of verilog.

To be clearer, FLI is properitary, MTI specific one, Recently VHPI has been approved as standard and that's very similar to VPI (PLI 2.0) of Verilog. See:

https://www.accellera.org/pressroom/2006/AccelleraVHDL072106.pdf

These days HVLs have come into the picture.... and either Specman-e or Vera is used for testbench purpose.....

But in future Vera is going to phase out... and System Verilog will take its place...

SystemVerilog has incorporated Vera's features but is more than Vera itself, it is a HDVL than HVL (unlike Vera). Also Synopsys doesn't seem to be "replacing" Vera in the near future. Both co-exist AFAIK.
Regards

Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

 

[hys]

Re: Verilog testbenches

Ajeetha,

I agree with u that VHDL has more capabilities as compared to plain verilog. But if you consider the normal testbench requirements, in my experience I havent seen much difference. However I have been using VHDL since many yrs.

Vera and System Verilog.....
Well that is debatable..... If my vendor is Synopsys and am looking at VCS, then I would always see SV over-shadowing Vera. I have been working with Vera recently and I know the problems involved in developing a RVM-vera based verification environment. At the same time I started looking at SV too... what I felt is that if I was given an option of using either SV or Vera in the beginning of the project, I would have chosen SV for sure. Things have very much simplified in SV than in vera. Its purely my opinion that Vera will be phased out virtually (though not officially by synopsys) as SV is more productive than Vera itself.

If you talk to any of the synopsys folks and tell them that u r using vera... the first response is "Why dont you use System Verilog ?" I've got this response many times..

Best Regards,
Harish

 

[srini.eda]

Re: Verilog testbenches

Harish,
This is Srini from SNPS.

Vera and System Verilog.....
Well that is debatable..... If my vendor is Synopsys and am looking at VCS, then I would always see SV over-shadowing Vera.

Very interesting view - but quite different from what's true, atleast as our official and customer driven position is. Many of our long time Vera users want to stick to Vera and migrate to SV only for new projects that too after some time. Advanced Vera users want more features than what's available in SystemVerilog (such as AOP, overloading etc.) and Vera is our vehicle to deliver these new features, get the customers going and then donate it to SV. As you may know, any change to an IEEE standard takes its own time and some of our customers just don't wait - they go ahead and use them with Vera/VCS today!

So as far as I see, SNPS is not phasing out Vera, we leave the choice to users.

I have been working with Vera recently and I know the problems involved in developing a RVM-vera based verification environment.

Please consult Synopsys support team for any such issues - if you are not doing it already. Agreed, it is a different language and hence may require a mindset change - after all it is not Verilog syntax, but capability wise it is quite good/powerful.

At the same time I started looking at SV too... what I felt is that if I was given an option of using either SV or Vera in the beginning of the project, I would have chosen SV for sure. Things have very much simplified in SV than in vera.

With due respect to your opinions, I've seen some customers saying the other way around. I remember reading that in Verificationguild a while ago, that user likes Vera syntax so much and dislikes SV. It is all opinion (and FWIW - I agree with you Harish, I'm more of SV favorite guy myself )

If you talk to any of the synopsys folks and tell them that u r using vera... the first response is "Why dont you use System Verilog ?" I've got this response many times..

Best Regards,
Harish

Not sure whom you spoke to "many times", I can confirm that this is not our stand. Please write to me @ svenkat <> synops.. may be their communication/messaging was incorrect (they perhaps intended to say some thing else).

Summary: Synopsys promotes both OV and SV equally and based on customer demand, vera has been growing in capabilities more than SV (for Verification).

Thanks and regards
Srini