Adding User ports for custom logic in EDK

[guduru]

Hi,
iam working on EDK Xilinx platform studio.I have added user logic to the opb bus in an embedded system using create and import peripheral wizard.my code has 2 input ports of 8 bit width.i have to give data to these two ports from the BRAM attached the OPB .i have noticed that there is an opb2ip bus to the user logic.can anybody help how to use this opb2ip bus to supply data to the two ports present in my userlogic? and how to add the external ports apart from those created using CIP wizard.
Thank u.

 

[shawndaking]

The Best Way Is Not To Use Any Wizard And Don't Use The Xilinx Horrable Cores.
Just Write A Pure VHDL Implementation And Attach It Directly To OPB Bus !

this is how your entity should look like :

entity your_entity is

generic (
C_BASEADDR : std_logic_vector ;
C_HIGHADDR : std_logic_vector;
C_OPB_DWIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_USER_ID_CODE : integer := 5;
C_READ_OPTIONAL_REGS : integer := 0
);
port (
-- OPB signals (Slave Side)
SOPB_Clk : in std_logic;
SOPB_Rst : in std_logic;
SOPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
SOPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
SOPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
SOPB_RNW : in std_logic;
SOPB_select : in std_logic;
SOPB_seqAddr : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;

-- OPB signals (Master Side)
MOPB_Clk : in std_logic;
MOPB_Rst : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
MOPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
MOPB_errAck : in std_logic;
MOPB_MGrant : in std_logic;
MOPB_retry : in std_logic;
MOPB_timeout : in std_logic;
MOPB_xferAck : in std_logic;

---------------------------------------------------------------------------
-- put your signals here
---------------------------------------------------------------------------
);