Implement carrier detection logic in FPGA

[pulkit.vlsi]

Hi,
I am working on an application where i need to implement carrier sense logic for and half duplex 10Base2 interface.

in one ieee document i got below detail:

147.3.7 Carrier Sense
When operating in half-duplex mode, the 10BASE-T1S PHY shall sense when the media is busy and convey this information to the MAC asserting the signal CRS on the MII as specified in clause 22.x. CRS is generated by PCS Receive as the logical OR of the “transmitting” and “receiving” variables.

Please help me understand this logic.

 

[FvM]

Ethernet PHY involves analog functions that can't be implemented with FPGA digital IO. How are you interfacing FPGA to 10BASE2 media?

 

[pulkit.vlsi]

FPGA will deal with digital part only. One side it is connected to MAC. other side it is connected to transformer which is further connected to a 10 base 2 transiver IC.

 

[FvM]

Which transceiver? Which signals are connecting the transceiver to FPGA? CRS generation is usually part of ethernet transceiver PHY.

 

[pulkit.vlsi]

Which transceiver? Which signals are connecting the transceiver to FPGA? CRS generation is usually part of ethernet transceiver PHY.

78Q8392L.

 

[FvM]

Carrier sense detection for 10BASE2 is performed in PLS unit, see 802.3 section 1 clause 7. Mentioned CRS signal is used e.g. in 10BASE-T.

--- Updated Dec 26, 2022 ---

You are quoting new 10BASE-T1S spec (single twisted pair ethernet), a completely different technology.