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VHDL or VERILOG?adder in ise12.1 shematic
how can i use 24 bit adder with enable pin in ise 12.1?
cant you write a vhdl or verilog code for the same??
VHDL or VERILOG?
See some examples in language templates
in ISE EDIT--> language templates
In that VHDL or VERILOG-->Synthesis constructs--> Coding examples --> ARithmetic --> Add/Sub
or you are talking about Schematic's in ISE??
first=if en=1 then c <= a+bis very difficalt? if en = '0' then c <= a+b
well if you build it yourselfI build it yourself/
COMPONENT summ
PORT(
a : IN std_logic_vector(23 downto 0);
b : IN std_logic_vector(23 downto 0);
en : IN std_logic;
c : OUT std_logic_vector(23 downto 0)
);
END COMPONENT;
Inst_summ: summ PORT MAP(
a => ,
b => ,
en => ,
c =>
);
////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity summ is
Port ( a : in STD_LOGIC_VECTOR (23 downto 0);
b : in STD_LOGIC_VECTOR (23 downto 0);
en : in STD_LOGIC ;
c : out STD_LOGIC_VECTOR (23 downto 0));
end summ;
architecture Behavioral of summ is
begin
adder_en : process( en ) is
begin
if en = '1' then
c <= a + b;
end if;
end process adder_en;
end Behavioral;
and design utilites / create schematic symbol
add symbol in schematic.sch
tnx a lot
i write it but i have some question
1=why you define it in process
you can define it in
architecture
2=and if en='0'
what happen?
3=why you use this library?
use IEEE.STD_LOGIC_ARITH.ALL;
you mean i cant use c <= a+b when en = '1';Yes you can, but you cannot use "if" outside of a process. You would need to write this instead:
c <= a+b when en = '1';
But the problem with this code, and the origional process, is that is creates a latch, and that is a bad thing. You need a clock, and for a clock it is recommended you use a process.
There is no need to in this case, many designers and code gen tools add it by default.
you mean i cant use c <= a+b when en = '1'; outside process?
by the way
is process sequential or concurrency type?
signal c : natural;
process
varible x: integer;
begin
x := 1;
x := x + 1;
c <= 1;
c <= c + 1;
end process;