Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
As you may know, 2's complement is just a representation of negative values/negation of values. 2's complemet of a value is 1's complement +1. (and 1's complemet is a plain bitwise inversion)
For adders, the process is not substantially affected, the only difference being which value causes an overflow -- when the result is too big for the word size and the polarity of result becomes wrong. So you may use the cookbook adders for that particular FPGA--usually well defined in the library of your logic compiler.
Substraction "a-b" can be written as "a+(-b)", and thus you have to produce 2's complement of "b". Because -b in 2's complement is just b inverted +1 (=NOT b +1): To get the result of "a-b", which can thus be described also as "a+(NOT b +1)" you may feed that extra "+1" to the carry in of your adder. Of course, the library modules usually have it all ready made, and often pretty well optimalized for the particular component.
The rest goes similar way, a bit number theory, common sense and logical thinking, and you can figure it out. And do not forget that reading documents, application notes, and "Googling" may bring a lot of useful knowledge.