without wire load model

[ASIC_intl]

wire load models, synthesis

Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.

Thanking,
ASIC

 

[lakshman.ar]

wireload model slope

synthesis & timing analysis without wireload models ????
AFAIK, Then the only available solution is to use
"Physical compiler" ( from Synopsys).

This tool can perform synthesis and STA ( pre-lyt) without the WLMs, cos the tool estimates the wire/net delays by virtually placing the cells during the synthesis stage !

please correct me if i m wrong !

WBR
Lakshman

 

[ASIC_intl]

zero wire load model

Hi Lakshman

I want to do synthesis only ( not timing analysis) without wire load model . Is it possible to do synthesis only in design compiler without wire load model? If yes then let me know.

If the synthesis can be done then I will come to know the critical paths in the design by using the report_timing command of design compiler.

Thanks

 

[iwpia50s]

read_lib

To do synthesis without WLM you need to create a WLM within your .lib with zero capacitance and zero resistance, or you can create it separately and load it as a .lib.

 

[lakshman.ar]

FOA y do u want to do a synth run without a WLM ????

i agree with the reply posted above .... creating ur own WLM within ur .lib with zero R & C !!!!

 

[ASIC_intl]

Hi
WLM does not contain only R and C. It also contains area, Slope,fanout_length. I can cfreate a WLM with R-C=0. But what should be the values I should put for area, Slope,fanout_length in that WLM.

Added after 5 hours 59 minutes:

Hi Lakshman

Suppose I want to create a zero wire load model in the library. My library is in binary format .db. So I am unable to modify the binary library including the zero WLM.

 

[iwpia50s]

Even if your library is binary you can still create a separate WLM and load it. This is not completely correct syntax wise, but use something like the following:

library(myWLM) {

/* zero wire-load */
wire_load("zero") {
resistance : 0;
capacitance : 0;
area : 1;
slope : 1;
fanout_length(1,2000);
}
}

 

[ASIC_intl]

Hi

I think the following parameters should be changed to zero in the wire load model as follows.

area : 0;
slope: 0;
fanout_length (1, 0);
fanout_length (2, 0);

How can I come to know the correct syntax of creating a library with only the wire load model?

Thanking

 

[ASIC_intl]

HI

I do not have license to read a .lib file while using dc. So even if I have zero WLM I cannot load it or read it in DC. What are the other alternatives to solve this?

 

[iwpia50s]

You can compile it yourself...there should be at least 1 lib_compile license.

 

[ASIC_intl]

No lib_license is available with me. What to do?

 

[eeeraghu]

for simply synthesizing and checking the timing reports, without any WLM use the clock uncertainity level to >20% so that whatever the delays & extra R C & other cancel out w r t WLM when there is >20% of uncertainity. Hope iam true.

 

[lakshman.ar]

@eeeraghu

hw is it possbile ????
at the pre-layout level, WLMs will be used in datapath and clock path correct ???
hw can delaying the clock be a solution for WLMs ???

 

[shiv_emf]

never heard this.
i should try this !! pls tell us adv of doing this ?

 

[iwpia50s]

Setting the clock uncertainty higher only makes timing more difficult to meet, it does not impact interconnect delays. Sound like you got your library from a vendor, they usually will provide a zero wireload model in the library for unit delay analysis. Check with your vendor.

 

[ASIC_intl]

Then what should be the solution?

 

[iwpia50s]

Where did you get you timing models? Is there any documentation? Can you contact the vendor or library group?

 

[ASIC_intl]

Hi iwpia50s

I tried to compile the .lib library using the read_lib command. But the design compiler says that you do not have library license to execute read_lib command. Do u mean this library license by your lib_compile license?

If u wanted to mean somet other license or some othe procedure please let me know.

Thanks.

 

[ramz]

without using wire load models in our script file ... the synthesis tool will take default wire load and then calculate the estimated delays of the paths..

wire load model is must for synthesis..
if wrong plz correct

 

[lakshman.ar]

WLM is a must for doing synthesis !!!!

@eeeraghu : pal, u listening or wat ????
can you please explain, hw does increasing the uncertainty of the clock help in not using the WLMs ????

infact as "iwpia50s" said, increasing the uncertainty in the clock makes ur timing ( hold time ) more stringent ...

now wer does increasing uncertainty and not using WLMs link ???