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[SOLVED] adder in ise12.1 shematic

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maia31

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how can i use 24 bit adder with enable pin in ise 12.1?
 

cant you write a vhdl or verilog code for the same??
 

maia31 said:
adder in ise12.1 shematic
how can i use 24 bit adder with enable pin in ise 12.1?
Click to expand...
VHDL or VERILOG?
See some examples in language templates
in ISE EDIT--> language templates
In that VHDL or VERILOG-->Synthesis constructs--> Coding examples --> ARithmetic --> Add/Sub




or you are talking about Schematic's in ISE??
 
Last edited:

i can
but i want in schematic form not vhdl form
and this is part of a bigger project
and ise schematic have 16 bit adder
but not 24 bit
and all of them don't have enable pin

---------- Post added at 08:33 ---------- Previous post was at 08:31 ----------
vipinlal said:
cant you write a vhdl or verilog code for the same??
Click to expand...

i can
but i want in schematic form not vhdl form
and this is part of a bigger project
and ise schematic have 16 bit adder
but not 24 bit
and all of them don't have enable pin

---------- Post added at 08:34 ---------- Previous post was at 08:33 ----------
sanju_ said:
VHDL or VERILOG?
See some examples in language templates
in ISE EDIT--> language templates
In that VHDL or VERILOG-->Synthesis constructs--> Coding examples --> ARithmetic --> Add/Sub




or you are talking about Schematic's in ISE??
Click to expand...

well im talk about Schematic's in ISE
and by the way may language is vhdl
 

is very difficalt? if en = '0' then c <= a+b
 

you have a problem just in the 12 ise
 

summ.JPG in ise 11
 

dose ise11 has 24bit adder or you build it yourself?
 

COMPONENT summ
PORT(
a : IN std_logic_vector(23 downto 0);
b : IN std_logic_vector(23 downto 0);
en : IN std_logic;
c : OUT std_logic_vector(23 downto 0)
);
END COMPONENT;

Inst_summ: summ PORT MAP(
a => ,
b => ,
en => ,
c =>
);



////////////////////


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity summ is
Port ( a : in STD_LOGIC_VECTOR (23 downto 0);
b : in STD_LOGIC_VECTOR (23 downto 0);
en : in STD_LOGIC ;
c : out STD_LOGIC_VECTOR (23 downto 0));
end summ;

architecture Behavioral of summ is

begin
adder_en : process( en ) is
begin
if en = '1' then
c <= a + b;
end if;
end process adder_en;

end Behavioral;


and design utilites / create schematic symbol

add symbol in schematic.sch
 
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    maia31

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treqer said:
COMPONENT summ
PORT(
a : IN std_logic_vector(23 downto 0);
b : IN std_logic_vector(23 downto 0);
en : IN std_logic;
c : OUT std_logic_vector(23 downto 0)
);
END COMPONENT;

Inst_summ: summ PORT MAP(
a => ,
b => ,
en => ,
c =>
);



////////////////////


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity summ is
Port ( a : in STD_LOGIC_VECTOR (23 downto 0);
b : in STD_LOGIC_VECTOR (23 downto 0);
en : in STD_LOGIC ;
c : out STD_LOGIC_VECTOR (23 downto 0));
end summ;

architecture Behavioral of summ is

begin
adder_en : process( en ) is
begin
if en = '1' then
c <= a + b;
end if;
end process adder_en;

end Behavioral;


and design utilites / create schematic symbol

add symbol in schematic.sch
Click to expand...

tnx a lot
i write it but i have some question
1=why you define it in process
you can define it in
architecture
2=and if en='0'
what happen?
3=why you use this library?
use IEEE.STD_LOGIC_ARITH.ALL;
 

maia31 said:
tnx a lot
i write it but i have some question
1=why you define it in process
you can define it in
architecture
2=and if en='0'
what happen?
Click to expand...

Yes you can, but you cannot use "if" outside of a process. You would need to write this instead:

c <= a+b when en = '1';

But the problem with this code, and the origional process, is that is creates a latch, and that is a bad thing. You need a clock, and for a clock it is recommended you use a process.

3=why you use this library?
use IEEE.STD_LOGIC_ARITH.ALL;
Click to expand...

There is no need to in this case, many designers and code gen tools add it by default.
 
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    maia31

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TrickyDicky said:
Yes you can, but you cannot use "if" outside of a process. You would need to write this instead:

c <= a+b when en = '1';

But the problem with this code, and the origional process, is that is creates a latch, and that is a bad thing. You need a clock, and for a clock it is recommended you use a process.



There is no need to in this case, many designers and code gen tools add it by default.
Click to expand...
you mean i cant use c <= a+b when en = '1';
outside process?
by the way
is process sequential or concurrency type?
 

maia31 said:
you mean i cant use c <= a+b when en = '1'; outside process?
Click to expand...

Yes you can. You just cannot use "if"


by the way
is process sequential or concurrency type?
Click to expand...

Both. Statements inside a process are sequential, but processes are concurrent with each other. But it really depends if you're assigning signals or variables. Variables are updated immediatly, signals are updated the next time the process suspends.

so for this process:

Code: 
signal c : natural;

process
  varible x: integer;
begin
  x := 1;
  x := x + 1;

  c <= 1;
  c <= c + 1;
end process;

Because if the way signals and variables work in the above process, x will always be 2. c will incrememnt by 1 and constantly get higher because the second assignment overrides the first assignment.
 
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    maia31

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Yes! schemes should only be synchronous. I always write process if the conditionю. Programming style
 
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