Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vinodkumar

  1. V

    Clock Problem VHDL Spartan 3E (RS 232)

    query is not clear....put in proper way....
  2. V

    clk generation based on control - reg

    already i have shown the clock as an input which is 40MHz,but it is not synchronous with control signsl... i am having an approach where in 80MHz clock is generated using DCM and 12.5ns delay obtained from risisng edge of control signal 1's and 0's are stored already in a ROM, they will be...
  3. V

    clk generation based on control - reg

    i am looking for a syntheziable code
  4. V

    clk generation based on control - reg

    pls go through the attachment..
  5. V

    clk generation based on control - reg

    dear all, iam looking for a verilog code : in which the input control signal is a signal with pulse width of 1us and period of 10us, output signal should be logic 1 when control is zero and 40MHz clock when control signal is logic1 and clk should be assigned after 12.5ns of logic1 . attached...
  6. V

    jtag usb cable always green - reg

    Hello ALL< 1)i am using xilinx USB jtag cable,and led always showing green even not giving vref. 2)i am sure the usb cable is working becoz another demo board is working with the same. 3)when i am connecting to my custom board it is showing green and i am seing reference voltage to be at 1.5V...
  7. V

    modelsim6.2 with ise 12.4

    hello, As i know ISE12 will not support modelsim 6.2.you need PE version...
  8. V

    virtex-5-EDK - mb_opb - reg

    hello all, I am using virtex 5SX35T custom board in which i want to use microblaze for UART communication and protocol. even if i am writing simple code..it is not seen in hyperterminal... here is the code: #include "xparameters.h" #include "stdio.h" #include "xutil.h" int main (void) { //...
  9. V

    EDK and microblaze usage for uart - reg

    hello all, I want to implement RS422 protocol. Is the implementation of UART in verilog is better or using Xilinx EDk with microblaze for effiecient use of FPGA and clock synchronization. regards, vinod kumar.
  10. V

    bit rate ,clock - reg

    hi all, I want to transmit data at 1Mbps,then i need to generate a 1Mhz clock or 1.152Mhz.since 1Mbp = 115200bits. regards, vinod kumar
  11. V

    How to create a ROM using Verilog code?

    Re: ROM in verilog pls checck the site WELCOME TO WORLD OF ASIC
  12. V

    PCB layer stack-up considerations

    i designed in such a way that all signal layers are guarded by power supply or gnd planes.... example: 1)TOPLAYER 2)GND 3)signal1 4)power1 5)signal2 6)power2 7)signal3 8)bottom layer
  13. V

    Problem with Xylo-L FPGA overheating

    Re: overheated FPGA? earlier i faced the similar problem with fpgas,but my problem resolved when i removed PROM on board....some junk data going into FPGA from PROM on every reset ...but when i dump some program to fpga directly it use to work....I hope this may help...
  14. V

    Data path and control path example

    Any digital system can be seen as a data path and control path.. Data path deals with the operations or processing of data...where as control path deals with when that operation or processing should be performed.
  15. V

    ISE simulator v/s Modelsim

    hello, earlier i got problem when i am trying to view internal signals in Xilinx ISE simulator...
See more

Part and Inventory Search

Back
Top