clk generation based on control - reg

[vinodkumar]

dear all,
iam looking for a verilog code :
in which the input control signal is a signal with pulse width of 1us and period of 10us,
output signal should be logic 1 when control is zero and
40MHz clock when control signal is logic1 and clk should be assigned after 12.5ns of logic1 .
attached figure :

module(clk,control,latch_en);
input clk;//40MHz
input control;
output latch_en;

 

[lordgty]

The description is not clear. Please redefine the requirement in understandable way.

 

[vinodkumar]

pls go through the attachment..

 

[lordgty]

module test(clk, control, latch);
input clk;
input control;
output reg latch=0;

always @(control or clk)
begin
if(control == 1'b0)
begin
#12.5;
latch = 1'b1;
end
else
begin
#12.5;
latch = clk;
end
end



endmodule

 

[vinodkumar]

i am looking for a syntheziable code

 

[FvM]

i am looking for a syntheziable code

Yes, this could be assumed. There are two points:
- you need an input clock to your design
- if we presume, that the input clock is unrelated to the control signal, you can't easily achieve a fixed delay between control signal and output clock.

You can approximate the intended 12.5 ns delay by using a higher input clock or multiplying it with a PLL and divide it down, synchronized to the control signal.But the delay won't be exact.

 

[lordgty]

i am looking for a syntheziable code

I have synthesized the code using xilinx ise 8.2

 

[FvM]

I have synthesized the code using xilinx ise 8.2

But the delay statements don't work in synthesis.

 

[lordgty]

But the delay statements don't work in synthesis.

Yes sir, you are right. Now an actual hardware delay can be introduced by the use of counter. I will try that.

 

[vinodkumar]

already i have shown the clock as an input which is 40MHz,but it is not synchronous with control signsl...

i am having an approach
where in 80MHz clock is generated using DCM and
12.5ns delay obtained from risisng edge of control signal
1's and 0's are stored already in a ROM,
they will be read for alternate count of 80MHz clock....
here exact delays are possible i think...
but i am looking for better approach...


regards,
vinod kumar...

 

[FvM]

here exact delays are possible i think...

Delay of an asynchronous signal will be always inaccurate by an amount of a clock period at maximum. Presuming your FPGA has high frequency PLLs ("DCM"), you can multiply the clock frequency and reduce the delay error, as adresses in post #6. You can even create multiple phase shifted clock and select the best one on the fly. Or use logic cell delay chains in combination with the clock. It ends up in a rather complex design anyway.

 

[mrflibble]

Stupid question: what is this used for, and how precise must this 12.5 ns delay be?