ISE simulator v/s Modelsim

[rsabhilash]

Hello all,
I am trying to implement MAC core using Xilinx ISE 10.1.
Is it possible to simulate entire design in ISE simulator ?
Whether Modelsim is necessary for simulation.I need advice to proceed with my design.
Thanks in advance
Abhilash.R.S

 

[vipinlal]

I only use xilinx ise for simulation.It is quite good.I think it will be possible to simulate any design in ISE with a good testbench.
But at the same time I havent used ModelSim, so i dont know any advantages of ModelSim over xilinx ISE.

--vipin
https://vhdlguru.blogspot.com/

 

[vinodkumar]

hello,
earlier i got problem when i am trying to view internal signals in Xilinx ISE simulator...

 

[rsabhilash]

Is there any method to view internal signals .

 

[vipinlal]

Except variables all signals(internal signals also) can be viewed in xilinx ise. you just have to add them to the simulation window by dragging and dropping.

For ise 10.1 , on the left side click on simulation tab and you can find your module names in a hierarchical manner.click on the plus sign and you will be able to see more components in your design. Right click on the component and click on add signal to simulation window. Now re-run the simulation.

--vipin
https://vhdlguru.blogspot.com/

 

[rsabhilash]

Thanks for your immediate reply.
I am trying to simulate IP fifo generator in Xilinx ISE.
But it is not working.I can't read the data from fifo by pulling rd_en up.
What will be the problem

 

[vipinlal]

post the testbench code here.

 

[rsabhilash]

Test bench is given below

module fifo_test;

// Inputs
reg rd_en;
reg wr_en;
reg wr_clk;
reg rst;
reg rd_clk;
reg [7] din;
integer i = 0 ;
reg [8] stim[31] ;

// Outputs
wire full;
wire empty;
wire [7] dout;

// Instantiate the Unit Under Test (UUT)
fifo uut (
.rd_en(rd_en),
.wr_en(wr_en),
.full(full),
.empty(empty),
.wr_clk(wr_clk),
.rst(rst),
.rd_clk(rd_clk),
.dout(dout),
.din(din)
);

initial begin
// Initialize Inputs
$readmemh("input.vec",stim);
$display ("stim[0]=%b",stim[0]);
rd_en = 0;
wr_en = 0;
wr_clk = 1;
rst = 1;
rd_clk = 1;
din = 0;
#2 rst = 0;
for (i=0 ; i<20 ; i=i+1)
begin
#2 wr_en = 1 ;
din = stim ;
end
#2 wr_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;

#100 $finish ;
end
always
#1 wr_clk = ~wr_clk ;
always
#1 rd_clk = ~rd_clk ;
endmodule

Added after 12 minutes:

@pini_1
I am writing code in verilog .Is it possible to use GHDL for simulation

 

[vipinlal]

With my little bit knowledge on verilog, what I understood is you are trying to write 20 values into FIFO and then read the FIFO.I think the testbench is fine.
So what is the output you are gettin here?

 

[rsabhilash]

I didn't get any data in dout.

 

[imbichie]

is the data in the dout pins are unknown or zeros in

your case

 

[rsabhilash]

Hello,
The dout is zero,they are not unknowns.

 

[imbichie]

can you post the code here

 

[rsabhilash]

Here I am giving the program

My top module is tx_fifo.v
tx_fifo.v
module tx_fifo(din,wr_en,wr_clk,dout,rd_en,rd_clk,full,empty,rst
);
input [7:0] din ;
input wr_en ;
input wr_clk ;
input rst ;
input rd_en ;
input rd_clk ;
output [7:0] dout ;
output full ;
output empty ;

fifo u1 (
.din(din),
.wr_en(wr_en),
.wr_clk(wr_clk),
.rst(rst),
.rd_en(rd_en),
.rd_clk(rd_clk),
.dout(dout),
.full(full),
.empty(empty)
);
endmodule

IP core wrapper file fifo.v is instantiated as u1
fifo.v

module fifo( rd_en, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
);
input rd_en;
input wr_en;
output full;
output empty;
input wr_clk;
input rst;
input rd_clk;
output [7 : 0] dout;
input [7 : 0] din;


// synthesis translate_off

wire \BU2/U0/grf.rf/mem/tmp_ram_rd_en ;
wire \BU2/N22 ;
wire \BU2/N20 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000118_123 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000093_122 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000053_121 ;
.
.
.
.
.
GND \BU2/XST_GND (
.G(\BU2/rd_data_count [0])
);

// synthesis translate_on

endmodule

// synthesis translate_off

`timescale 1 ps / 1 ps

module glbl ();

parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;

wire GSR;
wire GTS;
wire PRLD;

reg GSR_int;
reg GTS_int;
reg PRLD_int;

//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;

reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;

reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;

reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;

assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;

initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end

initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end


endmodule
// synthesis translate_on


Test bench of tx_fifo.v is tx_fifo_test.v
tx_fifo_test.v

module tx_fifo_test;

// Inputs
reg rd_en;
reg wr_en;
reg wr_clk;
reg rst;
reg rd_clk;
reg [7:0] din;
integer i = 0 ;
reg [8:0] stim[31:0] ;

// Outputs
wire full;
wire empty;
wire [7:0] dout;

// Instantiate the Unit Under Test (UUT)
tx_fifo uut (
.rd_en(rd_en),
.wr_en(wr_en),
.full(full),
.empty(empty),
.wr_clk(wr_clk),
.rst(rst),
.rd_clk(rd_clk),
.dout(dout),
.din(din)
);

initial begin
// Initialize Inputs
$readmemh("input.vec",stim);
$display ("stim[0]=%b",stim[0]);
rd_en = 0;
wr_en = 0;
wr_clk = 1;
rst = 1;
rd_clk = 1;
din = 0;
#2 rst = 0;
for (i=0 ; i<20 ; i=i+1)
begin
#2 wr_en = 1 ;
din = stim ;
end
#2 wr_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;

#150 $finish ;
end
always
#1 wr_clk = ~wr_clk ;
always
#1 rd_clk = ~rd_clk ;

endmodule

This is the code.The output waveform is attached.

 

[imbichie]

in the output wave you can see na, your fifo is always empty, means nothing in your fifo. that is why the dout is zero. fifo write is mistacked i think.

 

[rsabhilash]

I think, for write operation just make wr_en=1 and din=data.
Is there any thing that I might have forgotten ?

 

[vipinlal]

Have you added the fifo.xco(not the .v file) file to the project?
Try to see the internal signals in the UUT(i mean FIFO), to make sure that they are assigned properly.

 

[imbichie]

view the fifo reg in the waveform, and make sure that the written data are there.

 

[rsabhilash]

@vipinlal
I didn't add fifo.xco file to the project.
Is it possible to view internal signal of IP core.How ?

 

[vipinlal]

I think you have to add the .xco file to the project.
Right click on the project name and add fifo.xco to the project.Remove the .v file if it is added to the project.