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Recent content by verilog2vhdl

  1. V

    generic case statement (scalable)

    This is in a generic register file generation and I have this code, when I synthesize, im getting a priority encode decoder. Is there any way I can avoid priority encoder/decoder for for loop? Else is there any way I can have a case statement which is scalable (dont know how many case...
  2. V

    what is the issue with this code? Need help in synthesis

    I see the following errors ... pls help me in solving this... # Error: [46839]: "C:decoder3x8.vhd", line 30: Non-static range. Continuing ... # Error: [46292]: Module work.decoder3x8(translated) cannot be compiled because it contains non-rtl constructs. Please check the log for warnings or...
  3. V

    why is this for loop not synthesizable

    The code has been modified as follows and still see the same for i in I_b'RANGE downto 1 LOOP O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1); END LOOP; I see the error as Illegal use of 'range/'reverse_range attribute
  4. V

    What is the difference between synthesis and physical synthesis?

    synthesis synthesis is conversion of rtl to high level gates physical synthesis is conversion of high level gates to transistor level logic
  5. V

    why is this for loop not synthesizable

    for loop is synthesizable for i in I_b'RANGE downto 0 LOOP O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1); END LOOP; I see the error as Illegal use of 'range/'reverse_range attribute
  6. V

    can someone help me in synthesis of the attached design

    It is giving errors .... Pls modify if needed...
  7. V

    bit_vector subtraction with constant function

    in which library do i get bit_vector subtraction with constant funtion?? can some one give me the code if possible... the need is i have SIGNAL O_cnt_xhdl1 : bit_vector(12 DOWNTO 0); and i want to do O_cnt_xhdl1 <= O_cnt_xhdl1 - "0000000000001"; I see the...
  8. V

    === equivalent in vhdl

    verilog === equivalent in vhdl??
  9. V

    $time equivalent in vhdl

    to_decstring in vhdl package I got the following code for vhdl WRITE(ERRORFILE, "time" & to_decstring(NOW) & ":"); from verilog of $fdisplay (ERRORFILE, "time%d:", $time); I get the error as No feasible entries for subprogram "to_decstring". in modelsim, what is the issue??
  10. V

    can someone help me in compiling the attached vhdl files

    also please let me know how to compile the librarires of xhdl in detail ... as im very new to vhdl pls help mee...
  11. V

    can someone help me in compiling the attached vhdl files

    i converted the designs with xhdl from verilog to vhdl, i see lot of syntax errors, any kind soul help me in fixing the errors for me...
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