verilog2vhdl
Newbie level 6

for loop is synthesizable
for i in I_b'RANGE downto 0 LOOP
O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1);
END LOOP;
I see the error as
Illegal use of 'range/'reverse_range attribute
for i in I_b'RANGE downto 0 LOOP
O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1);
END LOOP;
I see the error as
Illegal use of 'range/'reverse_range attribute