why is this for loop not synthesizable

[verilog2vhdl]

for loop is synthesizable

for i in I_b'RANGE downto 0 LOOP
O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1);
END LOOP;


I see the error as

Illegal use of 'range/'reverse_range attribute

 

[MGT78000]

is I_n(-1) defined?
or should you only go downto 1?

 

[verilog2vhdl]

The code has been modified as follows and still see the same

for i in I_b'RANGE downto 1 LOOP
O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1);
END LOOP;


I see the error as

Illegal use of 'range/'reverse_range attribute

 

[MGT78000]

should be I_b'LEFT, instead of I_b'RANGE, by the looks of it.
https://www.csee.umbc.edu/help/VHDL/attribute.html

 

[mukesh1981]

for i in I_b'RANGE LOOP
O_g_tmp(i - 1) <= I_b(i) XOR I_b(i - 1);

end loop;

If u want range attribute this is the correct syntax, for range attribute no need to write down to. It will take range according your bit vector.

 

[manasiw2]

Hi,
'range operator returns whole range of std_logic_vector hence no need to specify 'downto x'.
Which synthesizer you are using ?

Added after 1 minutes:

Hi,
'range operator returns whole range of std_logic_vector hence no need to specify 'downto x'.
Which synthesizer you are using ?

 

[amitgangwar_vlsi]

I_b'RANGE
you can use different attributes for that

for i in I_b'RANGE loop

if range of I_b is 7 downto 0 then you can use
for i in I_b'high downto 0 loop
for i in I_b'left downto 0 loop

if range of I_b is 0 to 7 then you can use
for i in 0 to I_b'high loop
for i in 0 to I_b'right loop