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$time equivalent in vhdl

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verilog2vhdl

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to_decstring in vhdl package

I got the following code for vhdl
WRITE(ERRORFILE, "time" & to_decstring(NOW) & ":");

from verilog of
$fdisplay (ERRORFILE, "time%d:", $time);

I get the error as
No feasible entries for subprogram "to_decstring".

in modelsim, what is the issue??
 

darylz

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I believe you need some user VHDL packages which include this function.
 

avimit

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Instead of
Code:
WRITE(ERRORFILE, "time" & to_decstring(NOW) & ":");
YOu can just write
Code:
WRITE(ERRORFILE, "time ");
WRITE(ERRORFILE, NOW);
It should work, if not ping me
Kr,
Avi
http://www.vlsiip.com
 

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