$time equivalent in vhdl

[verilog2vhdl]

to_decstring in vhdl package

I got the following code for vhdl
WRITE(ERRORFILE, "time" & to_decstring(NOW) & ":");

from verilog of
$fdisplay (ERRORFILE, "time%d:", $time);

I get the error as
No feasible entries for subprogram "to_decstring".

in modelsim, what is the issue??

 

[darylz]

I believe you need some user VHDL packages which include this function.

 

[avimit]

Instead of

WRITE(ERRORFILE, "time" & to_decstring(NOW) & ":");

YOu can just write

WRITE(ERRORFILE, "time ");
WRITE(ERRORFILE, NOW);

It should work, if not ping me
Kr,
Avi
http://www.vlsiip.com