generic case statement (scalable)

[verilog2vhdl]

This is in a generic register file generation and I have this code, when I synthesize, im getting a priority encode decoder. Is there any way I can avoid priority encoder/decoder for for loop? Else is there any way I can have a case statement which is scalable (dont know how many case expressions will be there beforehand)

---

Code dot - [expand]
1
2
3
4
5
6
7
8
9
10
11
1 for( int ii = 0; ii < MAX_REGISTERS; ii++ ) begin : register_loop$
  2   if( valid && ii == addr[ADDR_WIDTH-1:0] ) begin$
  3     if( cmd ) begin$
  4        // read register$
  5        read_data <= register[ii];$
  6     else$
  7       // write register$
  8       register[ii] <= write_data;$
  9     end$
 10   end$
 11 end$

---

How to people write generic register files, if they dont know the size and number of register before hand without priority logic?

 

[ads-ee]

Take a look at the examples near the end. You actually don't need a for loop to build a register file. (Though you'll need the loop to implement a reset to the entire RF)
https://courses.cs.washington.edu/courses/cse370/10sp/pdfs/lectures/regfile.txt