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Recent content by ssuchitav

  1. S

    Lvds driver:- cmfb loop speed

    Hi, even if cmfb loop bw=30MHz, I am able to see a proper operation@600MHz in transient simulations. another thought is given the huge size of the driver transistors, the cmfb opamp will be loaded with a huge cap. trying to achieve a higher bw here would require excessive current. any comments?
  2. S

    Lvds driver:- cmfb loop speed

    Hi, I am working on lvds driver design with a speed requirement of 600Mhz. Given this, how much speed the CMFB loop or AMP should have? If the driver is able to handle the 600Mhz input, should a 30Mhz bw amp be good enough? Please suggest.
  3. S

    CMFB Loop Instabilty OR Design Issue

    Thanks. I'll rework on this.
  4. S

    CMFB Loop Instabilty OR Design Issue

    I'll try this out. Btw, does a negative phase, not equal to -180, @gain=0dB i.e. UGB cause instability?
  5. S

    CMFB Loop Instabilty OR Design Issue

    Hi, Please see the AC response and the setup for the same. I have also attached the transient behaviour of the circuit. I forgot to mention about the termination in my original post. This can be seen in the setup. Best Regards
  6. S

    CMFB Loop Instabilty OR Design Issue

    Hi, I am trying to simulate the circuit shown in the attachment. An ideal OPAMP model (dc gain=100dB UGB=1G) is used for CMFB. The input is of 100MHz. The circuit is showing unexpected rail to rail swing instead of the expected across 1.25V. I have cheked the CMFB loop stabilty and it looks...
  7. S

    The relation between jitter and data rate

    Hi, Would like to know the relation between jitter and data rate. is the jitter increases if we increase the data rate ? thanks in advance.
  8. S

    LAYOUT : MOS connected to IO PADs

    Hi, I have some NMOS transistors with DRAIN connected to IO pads. As per ESD guide lines m putting RPO layer on the DRAINS to avoid current crowding, but it gives problem in the extraction of the other devices which are stacked with the same NMOS. Any clue here? thanks in advance.
  9. S

    Decoupilng CAPS - any criteriato selectthem ?

    Decoupilng CAPS Hi I need to place some decoupling capacitors in my design. Just want to know ,is there any criteria to select them? thanks in advance.
  10. S

    Guidelines for LVDS DRIVER layout

    Hi! What are the points to be taken care while doing LVDSTX driver layout? Any constraints coming from DSM processes on this? Thanks in advance.
  11. S

    how to print node capacitor in spectre?

    captab option in spectre captab option is there in analog environment also. there is a switch under analysis options,that you need to enable.
  12. S

    Why NMOS has snapback properties

    nmos snapback Is this BJT current is triggered by high electric field near the drain junction? which is so called J-E heating?
  13. S

    how to print node capacitor in spectre?

    spectre captab could you try the option captab=1, see if it works.
  14. S

    IC Layout in DSM Technologies

    layout matching techniques 32nm HI, Are the interdigitization or common centriod methods for device matching not fruitful in DSM processes(65/55/45)? especialy, should we spread fingers or should use devices only in the above mentioned arrangements? Thanks in advance.
  15. S

    Tspice: Help required

    Hi Just wnated to know how to get transistor bias point details in tspice. do we need to invoke some options like cadence? thanks in advance
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