IC Layout in DSM Technologies

[ssuchitav]

layout matching techniques 32nm

HI,

Are the interdigitization or common centriod methods for device matching not fruitful in DSM processes(65/55/45)?
especialy, should we spread fingers or should use devices only in the above mentioned arrangements?

Thanks in advance.

 

[mviswa]

dsm of transistors

all these interdigitization or common centroid methods are to used in drawing analog layout. if any analog blocks present in the DSM process as to follow above techniques to improve the performance of analog circuit like sense amplifier , io buffer , level shifter etc.

if your chip contains only digital logic , then no need to follow above methods ..

HI,

Are the interdigitization or common centriod methods for device matching not fruitful in DSM processes(65/55/45)?
especialy, should we spread fingers or should use devices only in the above mentioned arrangements?

Thanks in advance.

 

[sat]

dsm of transistors analogue

As of date [2008], I am not aware of any TSMC UMC CHRT Analog or MS process for 65/45/32nm.
Variability is a huge concern - and as long it is not brought under foundry's control - Analog blocks will not be able to take advantage of miniaturization beyond 90nm .

 

[deepak242003]

stress + transistor + layout

as long as 65 is considered, these techniques are still fruitful.. but more effect including STI stress and well proximity and other similar effect dont allow the sharing of transistors....

 

[sandeep_torgal]

ic dsm

as long as 65 is considered, these techniques are still fruitful.. but more effect including STI stress and well proximity and other similar effect dont allow the sharing of transistors....

Am still not clear how STI effects sharing of transistors for matching. Can you provide us some more info and if any doc available.

Regards,
Sandeep

 

[deepak242003]

dsm technologies

Am still not clear how STI effects sharing of transistors for matching. Can you provide us some more info and if any doc available.

Regards,
Sandeep[/quote]

as we go below 90 nm the size of diffusion decreases.as a result the impact of mechanical stress from STI plays important role in performance.. so for matching we have to see that the impact should be same for each transistor.. and for that Sa and Sb (refer LOD effect for Sa and Sb ) shuould be equal for each gate fingers... hence sharing cant be done at this technologies...

Added after 1 minutes:

our netconection doesnt permit to upload any doucment .... so....

 

[sandeep_torgal]

ic layout matching

Thanks for the info. What am wondering is does it really effect if I do a cross coupled matching with the devices shared.

A1 B1
B2A2

<----Sa---->A1<--------------------Sb-------------------->
<--------------------Sa-------------------->B1<----Sb---->
<----Sa---->B2<--------------------Sb-------------------->
<--------------------Sa-------------------->A2<----Sb---->

Does the effects not nullify and the avg stress both the transistors see should be the same?
Does the Sa and Sb vary vertically ? does it vary for different set of blocks with transistors having same L and W?

Regards,
Sandeep

 

[deepak242003]

Thanks for the info. What am wondering is does it really effect if I do a cross coupled matching with the devices shared.

A1 B1
B2A2

<----Sa---->A1<--------------------Sb-------------------->
<--------------------Sa-------------------->B1<----Sb---->
<----Sa---->B2<--------------------Sb-------------------->
<--------------------Sa-------------------->A2<----Sb---->

Does the effects not nullify and the avg stress both the transistors see should be the same?
Does the Sa and Sb vary vertically ? does it vary for different set of blocks with transistors having same L and W?

Regards,
Sandeep

good point sandeep,.. agree wiht you..
STI stress mainly effects your drain current.... So in current mirror,bias blocks etc ( where we genneraly implement interdigital matching) this effect will play a major role.......
let me know your opinion on this..