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Guidelines for LVDS DRIVER layout

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ssuchitav

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Hi!

What are the points to be taken care while doing LVDSTX driver layout? Any constraints coming from DSM processes on this?

Thanks in advance.
 

Re: LVDS DRIVER layout

LVDS is specified for 2.5-3.3V

So you need thick oxide devices and level translators for anything below 250nm.

There is also voltage scalable LVDS with double termination. It avoid the NMOS+PMOS differential receiver at receive side and also have lower power.
 

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