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vt vth nmos
Well in submicron process, when L decreases, the short-channel effects are more prominent. Consequently, effects like DIBL reduce the vth of the transistor. I have seen that vth changes with W in submicron technologies but I don't know the exact reason behind it. When the width is...
Hi all,
I know that my question is not exactly relevant for this forum category, but I have found that this one is much more active than the EDA software issues category. I am running out of time and need some urgent help. I am nearing a tapeout deadline and suddenly Spectre simulator is not...
I think the high and low references which are fed back are decided by the output swing of the integrator being used. This ensures that the integrator never saturates.
Yes gate capacitances don't reduce when you do fingering, but if you start drawing too wide gates, the gate starts looking like an RC ladder at high frequencies. The long gate might not affect the bias at all but the high-frequency transconductance of the MOS gets screwed up.
I guess most CMOS processes come with an ADS kit. If you can get hold of the ADS kit for this process, it should have the *.lay and *.slm files, which contain the properties of the various layers of the process. You can look at the substrate conductivity in these files.
I have (unsuccessfully) used IC-based high-speed switches upto 3.5 GHz on board. I think microstrip simply does not work well in such cases. I had to put a few RF switches on one board and the results turned out to be terrible. The signals were getting attenuated by more than 15-20dB. Finally...
Re: RF filter design
AT 60 GHz, you cannot use standard FR-4 (too lossy). Also, microstrip is not the way to go at such high frequencies. You should consider coplanar waveguide structures. Most on-chip T-lines at 60GHz are coplanar stripline structures. A good reference for on-chip transmission...
It's been a long time since I have designed microstrip-fed patch antenna. The basic idea if I remember is to find the right point for feed. The dimensions of the patch can be easily approximated from the calculations given in any standard antenna textbooks. The feed point can also be...
tutorial op amp
Do you want to design an opamp or an OTA? If you want to design an OTA, I suggest you google EE140 and EE240 class projects from UC Berkeley. There are quite a few design project reports online.
No...actually fingering reduces parasitic resistance and capacitance. It reduces parasitic capacitance by reducing the overall drain/source area and perimeter. Quantitatively, drain/source capacitance reduces by about half when you finger a MOS device by more than 4-5. Actually it also reduces...
As I said, the resistor can be placed to set the output bias to be equal to the input bias. Secondly, the gain of any amplifier is always within a small range of input. The range of this input can be shifted by changing the ratio of the pMOS to nMOS width.
I think a CMOS inverter with a feedback resistor between input and output should do the job. It would have enough current drive due to the addition of gm of the pMOS and nMOS and the resistor should set the output bias to be the same as the input bias.
For digital, surely CMOS is much lower in power consumption than bipolar.
But for analog, it depends. Even though bipolar draws base current, so does the collector or the drain of a MOS transistor. So there is always static power dissipation. Bipolar gives you much higher transconductance of...
Re: which tools are better for verification (DRC ,LVS and RC
I have used ASSURA and CALIBRE and both are quite good for DRC, LVS and RCX. Although I found CALIBRE to be quite painful when it comes to representation of some forms of LVS errors. Both these tools are widely used in industry and...
Design of mixers for 24GHz, 60GHz and 77GHz applications is a hot topic. The bandwidths at these frequencies is about 6-7GHz. So the mixers have to be fairly wideband - both upconversion and downconversion.
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