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Well in submicron process, when L decreases, the short-channel effects are more prominent. Consequently, effects like DIBL reduce the vth of the transistor. I have seen that vth changes with W in submicron technologies but I don't know the exact reason behind it. When the width is too small (comparable to L), then there is something called narrow-width effect, which reduces the vth of the device.
For short channel Vth vs. W and L correlated with process type. I think vth increase while w decrease may be a shallow trench isolation. The parasitic capacitor at the width direction ends get more weight when the width get narrow.
In simple terms...., A channel is a conducting path for carriers from source to drain....and as we define threshold voltage as the minimum gate voltage required to form a conduction path....and as channel decreases the gate voltage required o turn on the device decreases...thus vth also decreases...
I don't think so!
Actually, Vth is almost nondepent on L or W when L or W is large (not short or narrow MOS). However When L or W decrease, the Vth would increase. You will see the reason and the formula on Neman's book, sorry, I can't remember the exact name of the book, it's on semiconductor device.
Actually, we can deduce the result from foundry's process file. It tells us if you want to use low vth process, we could not use minimun L any more, but use several times of the minimun L.
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