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Recent content by souvikedaboard

  1. S

    Importing delay paths generated from Primetime to tetramax

    Hi all, So I want to import the delay paths generated from Primetime to Tetramax. So I am using these commands: source pt2tmax.tcl write_delay_paths -clock clk -slack 10 -max_paths 1 -delay_type max <file_name> But when I am entering this particular command the file that is generated just...
  2. S

    Reporting critical path in Synopsys Primetime

    Hi all, So I have a combinational ckt(Benchmark c432 ckt to be precise) and I want to find out its critical path using Synopsys Primetime, because it is a combinational circuit it does not have a clock so after reading the design I used the create_clock command in primetime to set up a virtual...
  3. S

    Finding critical path in a combinational block

    Hey all, I was just wondering if I can find out the critical path of a big combinational circuit using Synopsys Primetime or any other CAD tools? Thanks
  4. S

    RTL for a pipelined processor

    Any other websites other than opencores? I tried looking for the RTL for OpenRISC 1000 but didn't get that at opencores.org.. :(
  5. S

    Converting FPGA synthesizable design to ASIC synthesizable design

    I wanted to covert it to ASCI from FPGA, I guess what you said converts it to FPGA from ASIC. Correct me if I am wrong
  6. S

    RTL for a pipelined processor

    Hey all I am looking for the RTL for a pipelined processor which can be synthesized using the Synopsys DC compiler(ASIC synthesizable) any suggestions from anyone as to where can I get these from?
  7. S

    Converting FPGA synthesizable design to ASIC synthesizable design

    Hey can anyone tell me the ways to convert a verilog RTL code which is FPGA synthesizable to ASIC synthesizable design so that I can use the Synopsys DC compiler, one of which I know is to use a reset signal? What are the others?
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    Unable to start the DVE gui for Synopsys VSC

    Hi, so I wrote the veriloge code for a counter and a testbench for it. However I am not able to start the DVE gui for it. When I am typing the dve command it keeps saying: Error-[DVAP021] DVE Cannot connect to X server Please check your display setting Any ideas about what can be done? I tried...
  9. S

    Design Compiler problems

    i have also tried using:- read_verilog {rtl verilog code filename include filname} - - - Updated - - - I called the `include file in the verilog code using full path I also included the full path while using read_verilog..... however it is still giving errors that the parameters declared in...
  10. S

    Design Compiler problems

    In my rtl verilog code I have included another file with " `include " which contains all the parameters and functions that are needed in the verilog code. However while synthesizing(reading using read_verilog) the RTL verilog code in Design Compiler I am getting errors like symbol "SVC" not...
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