Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reporting critical path in Synopsys Primetime

Status
Not open for further replies.

souvikedaboard

Newbie level 6
Joined
Feb 28, 2015
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
75
Hi all,
So I have a combinational ckt(Benchmark c432 ckt to be precise) and I want to find out its critical path using Synopsys Primetime, because it is a combinational circuit it does not have a clock so after reading the design I used the create_clock command in primetime to set up a virtual clock(not sure if it is the right step). After that I am trying to find out the critical path by using the command:
report_timing -from[all_inputs] -to[all_outputs] -max_paths 1

But the report that is getting generated is giving me "no constrained paths".
Can anyone help me with the problem please?

Thanks
 

sharath666

Advanced Member level 2
Joined
Apr 4, 2011
Messages
552
Helped
126
Reputation
252
Reaction score
124
Trophy points
1,323
Location
India
Activity points
3,830
If it is a purely combinational circuit, it does not make any sense reporting a critical path as first of all there are no valid paths in this design. A path is defined as the route traced from the launch flop to the capture flop both of which are not present in this design.
 

Ashish Agrawal

Member level 3
Joined
Mar 24, 2015
Messages
60
Helped
8
Reputation
16
Reaction score
8
Trophy points
8
Activity points
502
Hi,
To constrain a feed through path (pure combo) use set_max_delay.
command:
set_max_delay delay_value [-from from_list] [-to to_list]
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top