Newbie level 6
Hey can anyone tell me the ways to convert a verilog RTL code which is FPGA synthesizable to ASIC synthesizable design so that I can use the Synopsys DC compiler, one of which I know is to use a reset signal? What are the others?
I wanted to covert it to ASCI from FPGA, I guess what you said converts it to FPGA from ASIC. Correct me if I am wrong
I noticed that too. Just convert any FPGA IP (memory, plls, trasceivers, etc) to whatever the ASIC vendor supplies in their libraries or what they generate from say memory compilers. If the FPGA was using some big IP core like a MAC you'll have to find a vendor to supply you with an equivalent piece of IP to replace them.
Your biggest problem is going to be verification of the resulting RTL. Most FPGA designs don't have the extensive testbenches used by ASIC engineers, so your coverage if there was a testbench will probably be no more than 50% of the design if you're lucky. Not a big confidence builder when you're going to be spending millions to tape out an ASIC.
Nope, Remember the 80:20 rule. The first 20% of your verification will give you 80% of your results. This is really closer to 90:10 so that any FPGA design can get into the high 90% with a reasonable effort. The only difference between ASIC and FPGA verification is that FPGAs are easy to verify in hardware so that has replaced some of the effort needed for those last couple of percentile. A lot of ASICs now use FPGAs to verify their code.