Design Compiler problems

[souvikedaboard]

In my rtl verilog code I have included another file with " `include " which contains all the parameters and functions that are needed in the verilog code. However while synthesizing(reading using read_verilog) the RTL verilog code in Design Compiler I am getting errors like symbol "SVC" not defined symbol "USR" not defined...However all of these are already included in the file that I have included in the RTL verilog code? I am using
Syntax:- read_verilog <RTL verilog code filename>

Is the above syntax all right? Or do I need to read the included files too.. If yes how?

 

[ads-ee]

how did you call out the `include file? relative path or full path?
Did you use a relative path from where read_verilog was launched?

If you didn't include a path then read_verilog will be looking for the file in the current working directory where read_verilog was launched.

I haven't worked with DC in a long time, but that's what I remember and that is how other tools work.

 

[souvikedaboard]

In my rtl verilog code I have included another file with " `include " which contains all the parameters and functions that are needed in the verilog code. However while synthesizing(reading using read_verilog) the RTL verilog code in Design Compiler I am getting errors like symbol "SVC" not defined symbol "USR" not defined...However all of these are already included in the file that I have included in the RTL verilog code? I am using
Syntax:- read_verilog <RTL verilog code filename>

Is the above syntax all right? Or do I need to read the included files too.. If yes how?

i have also tried using:- read_verilog {rtl verilog code filename include filname}

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I called the `include file in the verilog code using full path I also included the full path while using read_verilog..... however it is still giving errors that the parameters declared in the included file are not defined

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Hi ads-ee, I have specified full path both in `include line and also in the read_verilog command......any other suggestions?

 

[ads-ee]

You should post the include line and the output of the read_verilog command.

If you have `define SVC etc in the include file you can't use read_verilog separately on it, the next file you parse won't have the definition of the `define.

The other possibility is you aren't using `include and `define correctly. Can you post some example code that doesn't parse in the same fashion (something simple) so we can look at how you use `include and `define.