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Well the logic is simple...
input = 1, output = 1;
input = 0, output = 0;
input = x, output = 1;
I just want a synthesizable verilog code for this. When the condition on Don't care arises, then I want output to be 1...how can i write a synthesizable verilog code for this
hiii,
Is it possible make hard macro in cadence and then instantiate that hard macro in our verilog code and do the synthesis in RC in cadence. If Possible please tell me the procedure to do this.
i want a verilog code for the following logic in post synthesis simulation
when e = 1, output = 1
when e = 0, output = 0
when e = x, output = 1
I have tried casex and many more things but nothing is working in post synthesis simulation.Anyone tell me a verilog code to get the following...
thank you but I really don't know iD,iCLK,sD...can you please tell me what are they and in which version I can find them like System verilog or some other version of verilog. If suppose I have to find out more then what I shoud search as I am getting unregistered version and registered version.
if suppose I increase the frequency due to which there will be setup violation due to which there is metastability at the output of register and an unknown value appear could be don't care"X". Now I have to compare this don't care value with a valid value. Lets suppose
A = XXXX;
B = 1234;
C = A...
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