making a don't care to a valid value in post synthesis simulation

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if suppose I increase the frequency due to which there will be setup violation due to which there is metastability at the output of register and an unknown value appear could be don't care"X". Now I have to compare this don't care value with a valid value. Lets suppose
A = XXXX;
B = 1234;
C = A XOR B....

now since i am comparing A and B and here both are different, so output should be 1 and not don't care....IF i am using casex then it is working fine in pre synthesis simulation but in post synthesis simulation the answer is "X". so how can I generate a valid value through this comparision in post synthesis simulation.

 

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A = XXXX;
B = 1234;
C = A XOR B....

now since i am comparing A and B and here both are different, so output should be 1 and not don't care....IF i am using casex then it is working fine in pre synthesis simulation but in post synthesis simulation the answer is "X". so how can I generate a valid value through this comparision in post synthesis simulation.

XOR will only generate an output of 1 if A and B have opposite values of 1 and 0. Either value being X will generate and X on the output as it is now indeterminate if the output should be a 1 or 0. I think you need to review your Boolean bitwise operations. i.e. A XOR B is not the same operation as A /= B.