Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

designing of skewed inverters

Status
Not open for further replies.

smiley_09

Newbie level 4
Joined
Jan 26, 2015
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
54
How will I use either a high skew or low skew inverter in my design while writing a RTL code?
 

While writing RTL code, don't take the skew into consideration. It does not make sense. Skew will be considered in later phases of the front end flow.
 

The timing between any path is for rise_path vrs fall_path. The ideal situation would be the gates are sized in such a way that rise_delay = fall_delay. this rarely happens because of the stacking effect and other design considerations. The skewed inverters are used at the timing analysis level with parasitics to try to make the rise_fall and fall_paths as equal as possible.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top