how to resolve problem of metastability

[smiley_09]

how to solve metastability by writing a verilog code in post synthesis simulation?

 

[K-J]

how to solve metastability by writing a verilog code in post synthesis simulation?

You can't solve metastability by writing Verilog code. Post a question that is more specific to the design issue that you are trying to solve.

Kevin Jennings

 

[bking]

Maybe start here: https://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf

 

[Port Map]

In some cases, like one bit data, a simple registering may be helpful.

in the example code below, iD is registered then used in if statement.
in unregistered version, the if statement may work incorrect,
in the unregistered version of iD, both of oQ1 and oQ2 may be Set.

	process(iClk)
	begin
		if rising_edge(iCLk)then
			sD	<=iD;--removing metastability
			oQ1	<='0';
			oQ2	<='0';
			if(sD='1') then
			--if(iD='1') then--unregistered version
				oQ1	<='1';
			else
				oQ2	<='1';
			end if;
		end if;--Clk Rising
	end process;

 

[smiley_09]

In some cases, like one bit data, a simple registering may be helpful.

in the example code below, iD is registered then used in if statement.
in unregistered version, the if statement may work incorrect,
in the unregistered version of iD, both of oQ1 and oQ2 may be Set.

	process(iClk)
	begin
		if rising_edge(iCLk)then
			sD	<=iD;--removing metastability
			oQ1	<='0';
			oQ2	<='0';
			if(sD='1') then
			--if(iD='1') then--unregistered version
				oQ1	<='1';
			else
				oQ2	<='1';
			end if;
		end if;--Clk Rising
	end process;

thank you but I really don't know iD,iCLK,sD...can you please tell me what are they and in which version I can find them like System verilog or some other version of verilog. If suppose I have to find out more then what I shoud search as I am getting unregistered version and registered version.

 

[Port Map]

I Considered iClk as Clk input and iD as input and oQ1 and oQ2 as output.
sD is a register for registering iD by rising edge of (iClk).

I think the verilog code may be like this:

   reg  sD;
   
   always @(posedge iClk)
      sD	<=iD;
	oQ1 	<= 1b'0';
	oQ2 	<= 1b'0';

	if (sD)
         oQ1 <= 1b'1';
      else 
	oQ2 <= 1b'1';

 

[mdyusuf]

You just post design related topic or code. Here is not slow metastability writing. If you need I will help you.

 

[tggzzz]

how to solve metastability by writing a verilog code in post synthesis simulation?

You cannot solve metastability; that debate was settled 40 years ago.

You can only guarantee to resolve a metastable state by waiting for an arbitrarily long time.

For practical purposes the algorithm is that you wait for a clock cycle and sample, then resample that sample another clock cycle later. Hopefully the probability of that second sample being metastable will be so long that you will never observe it in your lifetime, but that depends on the clock period and the details of the flip-flop used.

If you can't write HDL code for the that algorithm, then you have other more pressing problems.

 

[mdyusuf]

Here are some examples:

ReadCheck: assert (data == correct_data)
else $error("memory read error")
Igt10: assert (I > 10)
else $warning("I has exceeded 10");