smiley_09
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i want a verilog code for the following logic in post synthesis simulation
when e = 1, output = 1
when e = 0, output = 0
when e = x, output = 1
I have tried casex and many more things but nothing is working in post synthesis simulation.Anyone tell me a verilog code to get the following logic.If possible, try to avoid using registers.use more combinational.
when e = 1, output = 1
when e = 0, output = 0
when e = x, output = 1
I have tried casex and many more things but nothing is working in post synthesis simulation.Anyone tell me a verilog code to get the following logic.If possible, try to avoid using registers.use more combinational.