smiley_09
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hiii,
Is it possible make hard macro in cadence and then instantiate that hard macro in our verilog code and do the synthesis in RC in cadence. If Possible please tell me the procedure to do this.
Is it possible make hard macro in cadence and then instantiate that hard macro in our verilog code and do the synthesis in RC in cadence. If Possible please tell me the procedure to do this.
