Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

macro mapping

omar97

Member level 1
Member level 1
Joined
Apr 1, 2024
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
245
hello all,
i have a problem in macro mapping.
i am using icc2 tool (synopsys).
i have a memory in design (SRAM macros).
i generated it from memory compiler then i used generated .lef and .db to get ndm fram view and use it in ic compiler II.
i finished the design and when writing gds i show in gds viewer (Klayout) that macros are not mapped well.
everything is mapped succefully but macros are not.
i see that a wide peace of metal 1 and 2 and 3 are a macros, there is no polysi, no diffusion, only a wide width of metal with no thing belw.
when i write gds in icc2 i give it a memory gds to map layers.
can anyone help me to solve this problem, and tell me is that flow is correct to use memory as a macros?
thanks alot
 
the memory macro should have its own gds, generated from the compiler. when exporting a gds from ICC, you should tell it to merge your design gds with the memory gds. Is this the procedure you followed?
 
Yes, I did exactly as you say
As example
Command : write_gds ....... - merge_files memory.gds
 
Hello.
i see that a wide peace of metal 1 and 2 and 3 are a macros, there is no polysi, no diffusion, only a wide width of metal with no thing belw.
If i correct understood - inside final gds there is no polysilicon and other layers of macro (except metal)?
Might be stupid question - there is no some errors in job log icc2 in write_gds?
Did you watched gds of macro? May be he initially generated like this (error of compiler).
and tell me is that flow is correct to use memory as a macros?
Yes, this right way.
 
Hello.

If i correct understood - inside final gds there is no polysilicon and other layers of macro (except metal)?
Might be stupid question - there is no some errors in job log icc2 in write_gds?
Did you watched gds of macro? May be he initially generated like this (error of compiler).

Yes, this right way.
Actually, there no errors or warning message during write_gds
Icc2 maps macros as it is a wide sheet of metal (about 75 um wide).
I tried to not give it a gds of memory and wait for any warning that is a missing cell, I found that there is no warning message appeared and it's mapped as it is a wide sheet of metal.

Actually, I don't know what I should I do??!!
There is many floating gates errors related to memories and other errors.

Can you tell me the flow of using macros from the beginning ?
 
I think this sheet of metal you see exported is blockage. It is not real. Now that would be problem #1, and still does not explain why the final gds has no memory macro. Try a more basic experiment, instantiate a design that is only a single memory. Export that gds. see what you get.
 
Still stupid question: did initial macro.gds contain all needed layers (poly, diff...)?
 
Still stupid question: did initial macro.gds contain all needed layers (poly, diff...)?
Yes, it has all layers.
I can see it in gds viewer (klayout)
--- Updated ---

I think this sheet of metal you see exported is blockage. It is not real. Now that would be problem #1, and still does not explain why the final gds has no memory macro. Try a more basic experiment, instantiate a design that is only a single memory. Export that gds. see what you get.
Yes it is a blockage in fram view.
But I want to get real shape in writing final gds.
 
Did you try this option "-lib_cell_view layout" ?
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top