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Recent content by shavakmm

  1. S

    Hercules DRC error: PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut)

    I am getting below error in Hercules DRC run. Can anybody explain about this error and also how to solve this? PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut) ... 2 violations found ERROR DETAILS #####--- ERR_SELECT -----------------------------------...
  2. S

    Hercules DRC error: PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut)

    I am getting below error in Hercules DRC run. Can anybody explain about this error and also how to solve this? PO.RL.1: ALLPOLY maximum length = 200000nm (after poly_sub cut) ... 2 violations found ERROR DETAILS #####--- ERR_SELECT...
  3. S

    How to convert .tlf or .alf to .lib in Cadence Ambit?

    Re: .tlf or .alf to .lib Even i think that it doesn't exists..... We needed it for some internal analysis.... may be should drop this idea :)
  4. S

    How to convert .tlf or .alf to .lib in Cadence Ambit?

    Re: .tlf or .alf to .lib You are true... But i am specifically searching for any method or script to do conversion of .tlf into .lib
  5. S

    issues in subchip integration to top level

    What are considerations we should look into when subchip/macro/IP is integrated to the top level? What are the major issues we may use?
  6. S

    How to convert .tlf or .alf to .lib in Cadence Ambit?

    Is there any method or command to convert .tlf or .alf to .lib in Cadence Ambit?
  7. S

    How to read Synopsys encrypted files in DC?

    As per my knowledge synopsys encrypted files are read automatically by all synopsys tools. But i am getting error; it says Unable to read the HDL (UID-59)...and those files are encrypted, provided by Synopsys Whats going wrong? Any clue?
  8. S

    constraint migration from 130nm to 90nm

    Its PowerPC based SoC.... We have soft core IPs. Deliverable (its little old !!) obtained are targeted for 130nm.... Now, same soft cores are used to implement SoC in 90nm..... so this is the background story...!!!
  9. S

    constraint migration from 130nm to 90nm

    i have slack of -0.6 (prelayout)......i must achieve zero !!! Hence i am thinking if i can have accurate (or almost accurate.....because nothing can be accurate..its all design specific !!) constraint value suitable for 90nm i may achieve better timing..... By the by i am synthesizing PowerPC...
  10. S

    constraint migration from 130nm to 90nm

    I have design for which i have constraints and scripts targeted for 130nm. Now my requirement is to target it to 90nm libs. Is there is any thumb rule to change those constraints written for 130nm design to 90nm compatible?
  11. S

    design FIR Filter in HDL-how to map graph to hardware design

    Re: FIR Filter Below link may be helpfull to u: https://asic-soc.blogspot.com/2008/06/fpga-implementation-of-fir-filter.html
  12. S

    insert pad for a design

    can anybody explain how to insert pad for a design?( for synopsys flow). Earlier we had command in Design Compiler-now it is obsolete.
  13. S

    65 nm Leakage Problem

    please refer: https://asic-soc.blogspot.com/2008/03/leakage-power-trends.html https://asic-soc.blogspot.com/2008/04/low-power-design-techniques.html
  14. S

    Physical design interview questions for a fresher(5points)

    asic physical design interview questions Please refer below link: https://vlsifaq.blogspot.com/search/label/Physical%20Design
  15. S

    Clock Tree Synthesis and RTL synthesis

    Re: Clock Tree Synthesis below article can help u better: https://asic-soc.blogspot.com/2007/10/clock-tree-synthesis-cts.html
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