constraint migration from 130nm to 90nm

[shavakmm]

I have design for which i have constraints and scripts targeted for 130nm. Now my requirement is to target it to 90nm libs. Is there is any thumb rule to change those constraints written for 130nm design to 90nm compatible?

 

[vikas_33]

I think if u r moving to 90 nm most probably frequency of the design will also increase.

 

[paulki]

Hi,
If you are a front-end guy, nothing need to worry on the Technology migration part (Same RTL Design and Verification Environment can be used).
Sometime frequency also will be same. (Most of the time with the Technology migration performance improvement in terms of Area/Speed/Power also would be a criteria).
If you are a back-end guy, the picture is different, everything you need to change, etc like TECH_Libs, Area, Power Calculations, Signal Integrity (SI), Yield etc.......


-Paul

 

[shavakmm]

i have slack of -0.6 (prelayout)......i must achieve zero !!!
Hence i am thinking if i can have accurate (or almost accurate.....because nothing can be accurate..its all design specific !!) constraint value suitable for 90nm i may achieve better timing.....

By the by i am synthesizing PowerPC processor as a part of bigger SoC

 

[Kazzam]

Hi i am curious as to know what are you designing.......
May i know what is it??????

I have design for which i have constraints and scripts targeted for 130nm. Now my requirement is to target it to 90nm libs. Is there is any thumb rule to change those constraints written for 130nm design to 90nm compatible?

 

[shavakmm]

Its PowerPC based SoC....
We have soft core IPs.
Deliverable (its little old !!) obtained are targeted for 130nm....
Now, same soft cores are used to implement SoC in 90nm.....
so this is the background story...!!!

 

[Kazzam]

great!!!! thanks for the information..........

Its PowerPC based SoC....
We have soft core IPs.
Deliverable (its little old !!) obtained are targeted for 130nm....
Now, same soft cores are used to implement SoC in 90nm.....
so this is the background story...!!!

 

[jbeniston]

i have slack of -0.6 (prelayout)......i must achieve zero !!!
Hence i am thinking if i can have accurate (or almost accurate.....because nothing can be accurate..its all design specific !!) constraint value suitable for 90nm i may achieve better timing.....

By the by i am synthesizing PowerPC processor as a part of bigger SoC

If you are not trying to increase the frequency - just keep your timing constraints the same. You should be able to achieve 0 slack easily, just by moving to 90nm.