Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

issues in subchip integration to top level

Status
Not open for further replies.
S

shavakmm

Member level 4
Joined
Oct 6, 2007
Messages
75
Helped
9
Reputation
18
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
1,705
What are considerations we should look into when subchip/macro/IP is integrated to the top level? What are the major issues we may use?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top