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thank you for your answer
i use only one BSCAN instantiation in my design instead of 2 but when i use chipscope the problem show
i use spartan3e and ise14.1
googling it but no answer found
please help me
hi all
my design use the jtag loader and chipscope the error occur in map process because
Number of BSCANs: 2 out of 1 200% (OVERMAPPED)
how can overcome this error?
when write this process to covere all case of ir(3 downto 1) the below error occur
process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin
case ir(3 downto 1) is
when "000"...
hi
can i call component inside the process
as shown
process(clk)
begin
u1:anything port map (clk,inp1,inp2,out1,out2............);
end process;
if no how can i call port map inside process or under condition ???
thank you advanced;
thank you for your answer
in my design in future this signal is update through JTAG loader i cann't declared as constant
is found anther way to overcame this warnings , how?
hi
my design is use fixed_pkg to find the mean value for two array (a and b) each 16 input
and when synthesize the deign the warning below produced
Xst:1781 - Signal <a> is used but never assigned. Tied to default value.
Xst:1781 - Signal <b> is used but never assigned. Tied to default...
thank you for your answer
the utilization summary from synthesis reports as shown below:
Selected Device : 3s500efg320-4
Number of Slices: 2902 out of 4656 62%
Number of Slice Flip Flops: 1161 out of 9312 12%
Number of 4 input...
help me please
in my design this error appear in place and route step
tha target device is spartan 3e and the ise is ise14.1
error: Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it...
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