error in place and route step

[sarmad88]

help me please
in my design this error appear in place and route step
tha target device is spartan 3e and the ise is ise14.1



error: Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If
you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try
again

and the utilization summary is show below:

why this error occurs and how can overcome this error please?

 

[rberek]

While your FPGA does not appear to be full, one concern is the 496 latches you have in your design. There should be 0. FPGA's don't have latches, and if you have them in the utilization report it is usually because of poor synchronous descriptions - I assume you did not intentionally add them.

Besides making simulation and actual real world behaviour not match, it may be throwing off the place and route because it is trying to build the latches out of the resources it does have. You really need to address the latch situation first. There is no point in trying to optimize the implementation of poor RTL.

Go through your synthesis reports to see if it reports inferred latches or poor synchronous descriptions or other similar warnings.

r.b.

 

[sarmad88]

While your FPGA does not appear to be full, one concern is the 496 latches you have in your design. There should be 0. FPGA's don't have latches, and if you have them in the utilization report it is usually because of poor synchronous descriptions - I assume you did not intentionally add them.

Besides making simulation and actual real world behaviour not match, it may be throwing off the place and route because it is trying to build the latches out of the resources it does have. You really need to address the latch situation first. There is no point in trying to optimize the implementation of poor RTL.

Go through your synthesis reports to see if it reports inferred latches or poor synchronous descriptions or other similar warnings.

r.b.

thank you for your answer

the utilization summary from synthesis reports as shown below:



Selected Device : 3s500efg320-4

Number of Slices: 2902 out of 4656 62%
Number of Slice Flip Flops: 1161 out of 9312 12%
Number of 4 input LUTs: 5190 out of 9312 55%
Number used as logic: 5189
Number used as Shift registers: 1
Number of IOs: 33
Number of bonded IOBs: 33 out of 232 14%
IOB Flip Flops: 32
Number of BRAMs: 9 out of 20 45%
Number of MULT18X18SIOs: 17 out of 20 85%
Number of GCLKs: 17 out of 24 70%



as shown above there is no latch found but when make implementation process for my design the latch is appear and error found in place and route process as shown below :
Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If
you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try
again
1-how can overcame this problem ?
1-can you take me simple example to make latch in VHDL code ?
2-how can reduce number of latch in my design?

 

[barry]

here's a latch:

process(data,enable)
begin
     if enable='1' then
           q<=data;
     end if;
end process;

to avoid generating a latch, you need to completely define IF statements, e.g.,

process(data,enable)
begin
     if enable='1' then
           q<=data;
     else
           q<='0';
     end if;
end process;

 

[rberek]

Barry beat me to the punch. Follow his example.

Additionally, you don't see latches in the utilization report because FPGAs have no latches to utilize. Go over the synthesis logs to find warnings related to inferred latches or poor synchronous descriptions or similar warnings. These warnings will list the particular register which is being inferred as a latch. Go find the RTL that you used to describe that register and adjust your code as Barry suggested.

Then resynthesize and when you have zero latches, see if you still have any implementation warnings. If you are still running out of resources, reset your implementation options to minimize area and see if that fixes it.

r.b.

 

[sarmad88]

Barry beat me to the punch. Follow his example.

Additionally, you don't see latches in the utilization report because FPGAs have no latches to utilize. Go over the synthesis logs to find warnings related to inferred latches or poor synchronous descriptions or similar warnings. These warnings will list the particular register which is being inferred as a latch. Go find the RTL that you used to describe that register and adjust your code as Barry suggested.

Then resynthesize and when you have zero latches, see if you still have any implementation warnings. If you are still running out of resources, reset your implementation options to minimize area and see if that fixes it.

r.b.

thank you but i don't know why the BUFGMUX is 17 from 24 ??
i use same clk signal in 17 process as a rising edge