Handling signal rate error in FPGA

[Igloo2]

Hi,

In my implementation, I have to sample input data bits and store it to process.
The data comes bit by bit on a single input pin.
The data rate is 10Mbps with 0.01% tolerance.
The sampling frequency is 160 MHz. This is generated inside the FPGA using clock conditioning.
The crystal oscillator used is 50Mhz +/-50 PPM.

What are the techniques to sample this data so the error caused by the signal rate tolerance can be handled ?
What is the effect of the crystal oscillator PPM on the sampling ?

Please guide.
Thanks

 

[FvM]

The problem is known as CDR (clock and data recovery). Data encoding must have certain properties to allow it, e.g. minimal number of signal edges and synchronization characters to detect frame boundary. Tolerable rate error depends on this parameters.

 

[Igloo2]

The problem is known as CDR (clock and data recovery). Data encoding must have certain properties to allow it, e.g. minimal number of signal edges and synchronization characters to detect frame boundary. Tolerable rate error depends on this parameters.

The data is a 10Base2 Ethernet packet with a preamble.
I can sample every bit, but there is a possibility that in the long run, due to signal rate error, I might receive 1 extra or less bit.
The max. number of bits in a packet will be 12208 bits (as per IEEE 802.3)

 

[dpaul]

@Igloo2
Ethernet packets have a CRC field. If a TCP structure is used, there is always a possibility of retransmission in case of errors. The PHY and MAC takes care of stuff.....you need to trust those designs.

I can sample every bit, but there is a possibility that in the long run, due to signal rate error, I might receive 1 extra or less bit.

That seldom happens, also depends how long is long run.

 

[KlausST]

Hi,

This is an asynchronous interface, thus you need some clock alignment.

Did you read about Manchester encoding? --> you need to.

When you look at the timing diagram you see to have an edge at every center of the transmitted bit.
--> use this as the alignment.

***

At the borders of every bit you may or you may not have an edge, thus you can´t use it as alignment.

***
I personally would not take the effort to code the whole ethernet interface. I´d rather use an external ETH chip. There are mana manufacturers with many different chips with different features, speed, interfaces...

Klaus