Signal is used but never assigned

[sarmad88]

hi
my design is use fixed_pkg to find the mean value for two array (a and b) each 16 input
and when synthesize the deign the warning below produced

Xst:1781 - Signal <a> is used but never assigned. Tied to default value.
Xst:1781 - Signal <b> is used but never assigned. Tied to default value.


the code is below :


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.fixed_pkg.all;
--library UNISIM;
--use UNISIM.VComponents.all;


entity operations is
Port ( clk : in STD_LOGIC;
selector:in std_logic;
mean_resultut std_logic_vector(16 downto 0));
end operations;






architecture Behavioral of operations is

type ram is array(0 to 15) of sfixed(4 downto -8);

--ex1
--A=[3.1 -1.6 1.12 -0.19 -10.111 0.4 2.2 -5.6 -12.7 3.8 4.66 -1.222 10.61 0.99 -1.31 9.87]

signal a:ram:=(
"0001100011010","1111001100110","0000100011111","1111100010111",
"1010111100100","0000001100110","0001000110011","1101001100110",
"1001101001101","0001111001101","0010010101001","1111011000111",
"0101010011100","0000011111101","1111010110001","0100111011111"
);
--
--
--
----B=[2.3 1.9 -1.1 -0.81 0.78 0.515 0.629 -3.23 11.6 -15.313 -2.9 0.1 -0.09 0.13 8.9 4.2]
--
--
signal b:ram:=(
"0001001001101","0000111100110","1111011100110","1111100110001",
"0000011001000","0000010000100","0000010100001","1110011000101",
"0101110011010","1000010110000","1110100011010","0000000011010",
"1111111101001","0000000100001","0100011100110","0010000110011"
);



signal count:integer range 0 to 16:=0;

signal accumlator_resultx,accumlator_resulty:std_logic_vector(16 downto 0);

begin


process(clk)

variable sum1:sfixed(8 downto -8);

begin

if(clk'event and clk='1') then

if(count=16)then
accumlator_resultx<=to_slv(sum1);
else
sum1:=resize(sum1+a(count),sum1);
end if;
end if;


end process;


process(clk)

variable sum2:sfixed(8 downto -8);

begin

if(clk'event and clk='1') then

if(count=16)then
accumlator_resulty<=to_slv(sum2);
else
sum2:=resize(sum2+b(count),sum2);
end if;
end if;


end process;


process(clk)

begin

if(clk'event and clk='1') then

if(count<16)then
count<=count+1;
end if;

end if;
end process;


process(selector,accumlator_resultx,accumlator_resulty)

begin

case selector is
when '0' => mean_result<=accumlator_resultx;
when others=> mean_result<=accumlator_resulty;
end case;

end process;

end Behavioral;

in the ISE14.1
please how can overcome this waring and
is this waring effect to my design when design is configure into FPGA device ???

 

[TrickyDicky]

You have made a and b a signal, which means you can update them, but like it says, you never do. I assume you're trying to build a rom?
In this case, declare a and b constant rather than signal and the warning will dissapear. But it shouldnt affect the design on FPGA.

 

[sarmad88]

You have made a and b a signal, which means you can update them, but like it says, you never do. I assume you're trying to build a rom?
In this case, declare a and b constant rather than signal and the warning will dissapear. But it shouldnt affect the design on FPGA.

thank you for your answer
in my design in future this signal is update through JTAG loader i cann't declared as constant
is found anther way to overcame this warnings , how?