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Recent content by ravindra kalla

  1. R

    plzzz help for architecture

    i have to make a paralle arcdhitecture in which i am using processing element (this processing element is used to calculate sum of absolute difference of two matrics).in first case i have to calculate absolute difference of 18 matrcs so i need to use 9 processing element(two matrics in each...
  2. R

    help!!!!!!!!! on architecture

    hi, i am making a architecture in which i am using processing element which used to calculate sum of absolute difference (SAD)of two matrics of size 4*4.In one case i have to calculate SAD of 18 matrics and in other case i have to calculate SAD of 10 matrics.So if i am using 9 processing...
  3. R

    Architecture with which SAD of matrix is calculated

    help!!!! on architecture hi, i am making a architecture in which i am using processing element which used to calculate sum of absolute difference (SAD)of two matrics of size 4*4.In one case i have to calculate SAD of 9 matrics and in other case i have to calculate SAD of 5 matrics.So if i...
  4. R

    help>did anybody here work on diamond search algorithm BM

    hi, i m doing my final year project on diamond searchblock matching motion estimation.did you work on this field then please send private message to me .i need some help. thanking you.
  5. R

    please did anybody here work on diamond search BME

    hi, did anybody here work on diamond search block matching motion estimation please help me and send PM to me. thanking you
  6. R

    inputs in spartan kit(its urgent)

    hi, I made a programe for block matching motion estimation.In this i have to compare the (4*4) matrics of current frame,with 18,(4*4) mtrics of search frame.each element of matrics is pixel value(containing 8 bit).In first clock cycle (1,1) element of all the matrics is going to the 19 inputs...
  7. R

    how to give input in FPGA kit

    hi, i made a architecture,in that 19 eight bit input and 15 bit output is their,and architecture will run for 16 clock cycle,and during every positive edge of clock i have to give 8 bit input in all 19 input pin.this progrme i simulated in verilog xilinx.now i want to implement it in sparten...
  8. R

    how to give input in spartan3 FPGA chip(its urgent)

    hi, i made a architecture,in that 19 eight bit input and 15 bit output is their,and architecture will run for 16 clock cycle,and during every positive edge of clock i have to give 8 bit input in all 19 input pin.this progrme i simulated in verilog xilinx.now i want to implement it in sparten...
  9. R

    How to use block RAM in Xilinx?

    CAN ANYBODY TELL ME,HOW TO USE BRAM IN XILINX. PLEASE SEND ME GOOD REFERENCES. PLEASE ALSO TELL HOW TO STORE ANY VALUE IN BRAM. THANKING YOU HAVE A NICE DAY
  10. R

    What is block RAM and how to use it in Xilinx devices?

    CAN ANYBODY TELL ME,HOW TO USE BRAM IN XILINX. PLEASE SEND ME GOOD REFERENCES. PLEASE ALSO TELL HOW TO STORE ANY VALUE IN BRAM. THANKING YOU HAVE A NICE DAY
  11. R

    error in verilog code(its urgent)

    iteration limit reached debug verilog hi, please tell me about the error--------Error: (vsim-3601) Iteration limit reached at time 60ns",this is occure in my verilog simulation
  12. R

    How to run architecture 256 times in verilog(it is very urge

    Re: How to run architecture 256 times in verilog(it is very yes i want to trigger architecture 256 times so that some operation can perform sequentialy. please reply soon
  13. R

    How to run architecture 256 times in verilog(it is very urge

    hi, I have code an architecture in verilog.I want to run this architecture 256 times,how can i do this.If i put always are any loop then i can not call architecture inside this.SO please tell me how can i run architecture 256 times. it is very urgent for me.
  14. R

    comparator(its urgent)

    hi semiconductorman, can u explain your view clear.i m not able to understabd
  15. R

    comparator(its urgent)

    hi, i m making comparator tree for comparision of 9 value.i made a componnet (instantiation)for comparision of two value.now i want to call this component in my comparator tree.Comparator tree should be active when control signal will be high. for this i m using always...

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